KMAC/MASKED Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.365m	30.220ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.440s	36.233us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.450s	19.989us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.520s	6.559ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.280s	757.184us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.990s	82.947us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.450s	19.989us	20	20	100.00
		kmac_csr_aliasing	9.280s	757.184us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.120s	13.337us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.910s	135.528us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.431m	191.703ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.552m	39.858ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.287m	83.794ms	5	5	100.00
		kmac_test_vectors_sha3_256	35.938m	347.649ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.519m	395.628ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.686m	192.273ms	5	5	100.00
		kmac_test_vectors_shake_128	3.910m	46.681ms	5	5	100.00
		kmac_test_vectors_shake_256	32.639m	230.328ms	5	5	100.00
		kmac_test_vectors_kmac	4.220s	413.526us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.100s	514.929us	5	5	100.00
V2	sideload	kmac_sideload	7.733m	97.411ms	50	50	100.00
V2	app	kmac_app	6.207m	65.776ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.529m	30.362ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.183m	63.520ms	50	50	100.00
V2	error	kmac_error	8.202m	15.314ms	50	50	100.00
V2	key_error	kmac_key_error	17.410s	1.818ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.740s	1.708ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.920s	5.727ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.760s	1.235ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.457m	57.893ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	51.620s	6.281ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.894m	409.462ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.250s	165.868us	50	50	100.00
V2	alert_test	kmac_alert_test	1.310s	192.202us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.430s	961.257us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.430s	961.257us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.440s	36.233us	5	5	100.00
		kmac_csr_rw	1.450s	19.989us	20	20	100.00
		kmac_csr_aliasing	9.280s	757.184us	5	5	100.00
		kmac_same_csr_outstanding	3.020s	106.380us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.440s	36.233us	5	5	100.00
		kmac_csr_rw	1.450s	19.989us	20	20	100.00
		kmac_csr_aliasing	9.280s	757.184us	5	5	100.00
		kmac_same_csr_outstanding	3.020s	106.380us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.960s	324.139us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.960s	324.139us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.960s	324.139us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.960s	324.139us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.650s	421.170us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.451m	6.283ms	5	5	100.00
		kmac_tl_intg_err	5.620s	1.019ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.620s	1.019ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	51.620s	6.281ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.365m	30.220ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.733m	97.411ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.960s	324.139us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.451m	6.283ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.451m	6.283ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.451m	6.283ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.365m	30.220ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	51.620s	6.281ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.451m	6.283ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.276m	14.121ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.365m	30.220ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.581m	16.913ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			937	940	99.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 3.kmac_stress_all_with_rand_reset.13395106473923936902864708302405681310295756683118480684244134679368990837609
      Line 362, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8664317205 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 8664317205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.kmac_stress_all_with_rand_reset.67736879335296876287915073991487783370794013284565769459819956337463846159975
      Line 326, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3969295358 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 3969295358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 6.kmac_shadow_reg_errors_with_csr_rw.96646497110296402706407220395886176847070428221379850194191192684978585354762
      Line 155, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  92082986 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2787427380 [0xa624c434] vs 0 [0x0]) Regname: kmac_reg_block.prefix_3 reset value: 0x0
        UVM_INFO @  92082986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---