MBX Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	2.267m	6.799ms	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	13.069us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	15.852us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	8.000s	159.499us	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	40.267us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	73.582us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	15.852us	20	20	100.00
		mbx_csr_aliasing	2.000s	40.267us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	3.050m	28.617ms	2	2	100.00
V2	mbx_max_activity	mbx_stress_zero_delays	33.000s	145.840us	0	2	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	1.017m	2.997ms	2	2	100.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	45.000s	5.918ms	5	5	100.00
V2	alert_test	mbx_alert_test	33.000s	20.796us	50	50	100.00
V2	intr_test	mbx_intr_test	2.000s	14.898us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.000s	751.294us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.000s	751.294us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	13.069us	5	5	100.00
		mbx_csr_rw	2.000s	15.852us	20	20	100.00
		mbx_csr_aliasing	2.000s	40.267us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	113.800us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	13.069us	5	5	100.00
		mbx_csr_rw	2.000s	15.852us	20	20	100.00
		mbx_csr_aliasing	2.000s	40.267us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	113.800us	20	20	100.00
V2		TOTAL			149	151	98.68
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	167.565us	20	20	100.00
		mbx_sec_cm	33.000s	32.754us	5	5	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			231	233	99.14

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.60405060256034553686164373879788600027226691184565837837493799076860294624124
      Line 126, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 145839647 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
        UVM_ERROR @ 145839647 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
        UVM_INFO @ 145839647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 1.mbx_stress_zero_delays.24096761198997601592589057319968912632866501023825840604226052198532475964467
      Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @  95222086 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  95222086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---