OTBN Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 1.083m 224.606us 0 1 0.00
V1 single_binary otbn_single 2.317m 1.111ms 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 26.868us 5 5 100.00
V1 csr_rw otbn_csr_rw 4.000s 49.501us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 349.642us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 22.492us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 12.000s 73.035us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 49.501us 20 20 100.00
otbn_csr_aliasing 4.000s 22.492us 5 5 100.00
V1 mem_walk otbn_mem_walk 47.000s 3.640ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 16.000s 411.638us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 59.000s 199.800us 0 10 0.00
V2 multi_error otbn_multi_err 1.050m 727.061us 0 1 0.00
V2 back_to_back otbn_multi 1.517m 193.356us 0 10 0.00
V2 stress_all otbn_stress_all 1.217m 329.285us 0 10 0.00
V2 lc_escalation otbn_escalate 45.000s 326.196us 22 60 36.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 13.000s 50.748us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 16.000s 58.210us 0 10 0.00
V2 alert_test otbn_alert_test 8.000s 21.279us 50 50 100.00
V2 intr_test otbn_intr_test 6.000s 24.306us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 9.000s 136.091us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 9.000s 136.091us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 26.868us 5 5 100.00
otbn_csr_rw 4.000s 49.501us 20 20 100.00
otbn_csr_aliasing 4.000s 22.492us 5 5 100.00
otbn_same_csr_outstanding 9.000s 43.919us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 26.868us 5 5 100.00
otbn_csr_rw 4.000s 49.501us 20 20 100.00
otbn_csr_aliasing 4.000s 22.492us 5 5 100.00
otbn_same_csr_outstanding 9.000s 43.919us 20 20 100.00
V2 TOTAL 166 246 67.48
V2S mem_integrity otbn_imem_err 14.000s 21.636us 1 10 10.00
otbn_dmem_err 20.000s 84.565us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 19.000s 90.716us 0 5 0.00
otbn_controller_ispr_rdata_err 13.000s 181.065us 0 5 0.00
otbn_mac_bignum_acc_err 13.000s 17.523us 0 5 0.00
otbn_urnd_err 7.000s 35.003us 1 2 50.00
V2S illegal_bus_access otbn_illegal_mem_acc 12.000s 17.535us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 8.000s 41.070us 0 2 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 21.642us 7 10 70.00
V2S tl_intg_err otbn_sec_cm 3.717m 1.879ms 2 5 40.00
otbn_tl_intg_err 51.000s 314.854us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 26.000s 1.760ms 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S prim_count_check otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_mem_scramble otbn_smoke 1.083m 224.606us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 20.000s 84.565us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 14.000s 21.636us 1 10 10.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 51.000s 314.854us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 45.000s 326.196us 22 60 36.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 14.000s 21.636us 1 10 10.00
otbn_dmem_err 20.000s 84.565us 0 15 0.00
otbn_zero_state_err_urnd 13.000s 50.748us 4 5 80.00
otbn_illegal_mem_acc 12.000s 17.535us 5 5 100.00
otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_scramble_key_sideload otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 14.000s 21.636us 1 10 10.00
otbn_dmem_err 20.000s 84.565us 0 15 0.00
otbn_zero_state_err_urnd 13.000s 50.748us 4 5 80.00
otbn_illegal_mem_acc 12.000s 17.535us 5 5 100.00
otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 45.000s 326.196us 22 60 36.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 14.000s 21.636us 1 10 10.00
otbn_dmem_err 20.000s 84.565us 0 15 0.00
otbn_zero_state_err_urnd 13.000s 50.748us 4 5 80.00
otbn_illegal_mem_acc 12.000s 17.535us 5 5 100.00
otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_data_reg_sw_sca otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 13.000s 20.959us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 11.000s 19.448us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 57.000s 376.946us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 57.000s 376.946us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 18.000s 57.546us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 16.000s 70.188us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 103.093us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 103.093us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 11.000s 38.749us 6 7 85.71
V2S sec_cm_data_mem_sec_wipe otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.517m 193.356us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 37.000s 133.429us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 2.317m 1.111ms 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.717m 1.879ms 2 5 40.00
V2S TOTAL 66 163 40.49
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.233m 1.295ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 297 585 50.77

Failure Buckets