98165ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 5.100s | 222.483us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 7.890s | 545.121us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 6.900s | 555.767us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 7.130s | 169.835us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 6.030s | 298.839us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 7.600s | 193.741us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 6.900s | 555.767us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 6.030s | 298.839us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 6.050s | 168.830us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.450s | 556.895us | 5 | 5 | 100.00 |
| V1 | TOTAL | 67 | 67 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 4.980s | 180.118us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 25.900s | 1.570ms | 20 | 20 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 9.720s | 226.319us | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 6.770s | 170.510us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 11.510s | 1.006ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 11.510s | 1.006ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 7.890s | 545.121us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 6.900s | 555.767us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 6.030s | 298.839us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.640s | 180.494us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 7.890s | 545.121us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 6.900s | 555.767us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 6.030s | 298.839us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.640s | 180.494us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 114 | 114 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 43.180s | 3.236ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.930m | 1.796ms | 0 | 5 | 0.00 |
| rom_ctrl_tl_intg_err | 1.071m | 566.599us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.930m | 1.796ms | 0 | 5 | 0.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 3.930m | 1.796ms | 0 | 5 | 0.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.930m | 1.796ms | 0 | 5 | 0.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.930m | 1.796ms | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 5.100s | 222.483us | 2 | 2 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 5.100s | 222.483us | 2 | 2 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 5.100s | 222.483us | 2 | 2 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.071m | 566.599us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| rom_ctrl_kmac_err_chk | 9.720s | 226.319us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 1.645m | 13.723ms | 16 | 20 | 80.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 43.180s | 3.236ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.930m | 1.796ms | 0 | 5 | 0.00 |
| V2S | TOTAL | 56 | 65 | 86.15 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 6.065m | 11.670ms | 20 | 20 | 100.00 |
| V3 | TOTAL | 20 | 20 | 100.00 | |||
| TOTAL | 257 | 266 | 96.62 |
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
8.rom_ctrl_corrupt_sig_fatal_chk.18675353397279150087814771577664493292091151824752795389995499207975894806805
Line 107, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 10265793506 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 10265793506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rom_ctrl_corrupt_sig_fatal_chk.86371432076158572469826119221672973937004058828170643851283099185127562839947
Line 78, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 183260938 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 183260938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 3 failures:
0.rom_ctrl_sec_cm.85160613151847783199799215449072188342018211843848022051789734686715712064871
Line 182, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 48761101ps failed at 48761101ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 48761101ps failed at 48761101ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
1.rom_ctrl_sec_cm.15894420835478498214382857155245618272375692023513109604959768111129699379494
Line 303, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 129184231ps failed at 129184231ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 129184231ps failed at 129184231ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
... and 1 more failures.
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
3.rom_ctrl_sec_cm.23836265662808066793713019135774447693815948272625825218234861022895689644464
Line 173, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 41900796ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 41900796ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 41900796ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
4.rom_ctrl_sec_cm.61654013666493874151089306926315527766968910385729584996120769388232410064544
Line 285, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 56632217ps failed at 56632217ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 63332218ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 63332218ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))