ROM_CTRL/64KB Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.260s	2.344ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.250s	1.049ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	13.810s	2.506ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.590s	1.025ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.940s	295.839us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.770s	309.309us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	13.810s	2.506ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.940s	295.839us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.480s	336.975us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.440s	1.587ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	10.170s	1.334ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	54.450s	15.847ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.040s	2.104ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	15.430s	4.142ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.550s	461.277us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.550s	461.277us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.250s	1.049ms	5	5	100.00
		rom_ctrl_csr_rw	13.810s	2.506ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.940s	295.839us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.130s	314.262us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.250s	1.049ms	5	5	100.00
		rom_ctrl_csr_rw	13.810s	2.506ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.940s	295.839us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.130s	314.262us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.030m	23.698ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.034m	2.404ms	2	5	40.00
		rom_ctrl_tl_intg_err	2.398m	5.006ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.034m	2.404ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.034m	2.404ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.034m	2.404ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.034m	2.404ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.260s	2.344ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.260s	2.344ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.260s	2.344ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.398m	5.006ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
		rom_ctrl_kmac_err_chk	30.040s	2.104ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.574m	5.051ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.030m	23.698ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.034m	2.404ms	2	5	40.00
V2S		TOTAL			62	65	95.38
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.648m	17.408ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			263	266	98.87

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 3 failures:
  • Test rom_ctrl_sec_cm has 3 failures.

    • 0.rom_ctrl_sec_cm.107029431705746969240384638735662862697243779056264136868058095552907948612184
      Line 108, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 8759112ps failed at 8759112ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8759112ps failed at 8759112ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 1.rom_ctrl_sec_cm.84325313797769132642576541405698592267578639927074020981589327708679280049461
      Line 306, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 59620807ps failed at 59620807ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 59620807ps failed at 59620807ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 1 more failures.