98165ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.650s | 906.835us | 20 | 20 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.930s | 184.676us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.930s | 19.320us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.370s | 185.137us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.030s | 54.740us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.590s | 111.729us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.930s | 19.320us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.030s | 54.740us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 17.990s | 1.353ms | 2 | 20 | 10.00 |
| V2 | disabled | rv_timer_disabled | 3.610s | 2.842ms | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 22.398m | 6.471s | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 22.398m | 6.471s | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 6.030s | 12.466ms | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.880s | 49.180us | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.920s | 17.200us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.200s | 612.953us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.200s | 612.953us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.930s | 184.676us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.930s | 19.320us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.030s | 54.740us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.100s | 43.332us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.930s | 184.676us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.930s | 19.320us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.030s | 54.740us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.100s | 43.332us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 192 | 210 | 91.43 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.950s | 297.542us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.920s | 105.294us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.920s | 105.294us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.900s | 63.258us | 4 | 10 | 40.00 |
| V3 | max_value | rv_timer_max | 1.470s | 85.077us | 0 | 10 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.286m | 14.796ms | 15 | 20 | 75.00 |
| V3 | TOTAL | 19 | 40 | 47.50 | |||
| TOTAL | 311 | 350 | 88.86 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 24 failures:
0.rv_timer_min.8204894814746001554888289093482447208711649682384786729733943795007267479366
Line 75, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 63257665 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe2adb904) == 0x1
UVM_INFO @ 63257665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_min.3085940657409039212920271861559831129642391452827326918957783075414035324232
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
UVM_FATAL @ 203992807 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdc66d704) == 0x1
UVM_INFO @ 203992807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
0.rv_timer_random_reset.64708353812836588427302538959724094319600102064430993174567590971528650406836
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 370466034 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xeae75f04) == 0x1
UVM_INFO @ 370466034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_random_reset.11340635094732030358506680864530653751718485717965898432429335839145578881656
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 129656159 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x59a7d04) == 0x1
UVM_INFO @ 129656159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
0.rv_timer_max.103932487644390417489911889489042699869157158713571132195665090480819104106715
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 59347643 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 59347643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_max.26151776270983941493683597937639799959710557817015674864115972717496669662974
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 42735015 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 42735015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 4 failures:
2.rv_timer_stress_all_with_rand_reset.11497739540898601636468991472591371906717593809435018881225126828611228094290
Line 133, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2465141054 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2465141054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_timer_stress_all_with_rand_reset.42393671405080615015866614233023205480463763232033441448703589507357056020029
Line 77, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 40937187 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 40937187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
15.rv_timer_stress_all_with_rand_reset.97784835551988070229961851874545782782112597725839144369719254410807029817931
Line 336, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4074307573 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4074307573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---