SPI_DEVICE/1R1W Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.606m	58.158ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.850s	192.691us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.930s	105.407us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.120s	1.907ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.940s	2.635ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.890s	748.871us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.930s	105.407us	20	20	100.00
		spi_device_csr_aliasing	21.940s	2.635ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	14.502us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	46.434us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.230s	60.525us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	3.320us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.090s	3.174us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.250s	170.934us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.250s	170.934us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.010s	13.705ms	50	50	100.00
		spi_device_tpm_sts_read	1.540s	345.549us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	47.290s	42.253ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.950s	6.167ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.930s	11.204ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.930s	11.204ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	39.930s	4.383ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	39.930s	4.383ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	39.930s	4.383ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	39.930s	4.383ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	39.930s	4.383ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.000s	64.828ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.062m	67.417ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.062m	67.417ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.062m	67.417ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.580s	29.871ms	50	50	100.00
		spi_device_read_buffer_direct	17.170s	1.852ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.062m	67.417ms	50	50	100.00
		spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.589m	64.796ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.710s	2.944ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	19.710s	2.944ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.606m	58.158ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.595m	78.211ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.158m	169.382ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	16.739us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.150s	129.266us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.760s	82.533us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.760s	82.533us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.850s	192.691us	5	5	100.00
		spi_device_csr_rw	2.930s	105.407us	20	20	100.00
		spi_device_csr_aliasing	21.940s	2.635ms	5	5	100.00
		spi_device_same_csr_outstanding	4.510s	199.501us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.850s	192.691us	5	5	100.00
		spi_device_csr_rw	2.930s	105.407us	20	20	100.00
		spi_device_csr_aliasing	21.940s	2.635ms	5	5	100.00
		spi_device_same_csr_outstanding	4.510s	199.501us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.760s	96.223us	5	5	100.00
		spi_device_tl_intg_err	23.700s	1.922ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.700s	1.922ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	51.116m	1.500s	47	50	94.00
		TOTAL			1127	1151	97.91

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.84770880477154724451229082930493946736413860348235536891246293949471564171745
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4412081 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[16])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4412081 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4412081 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.82955387506518802988729484115539999035695888571201746474694333775370510237750
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1721925 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[97])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1721925 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1721925 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.75099062364130282473020452237628862175785114881465117169240826282361272034279
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    810666 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa08ff6 [101000001000111111110110] vs 0x0 [0])
        UVM_ERROR @    822666 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc03d12 [110000000011110100010010] vs 0x0 [0])
        UVM_ERROR @    901666 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa94cbf [101010010100110010111111] vs 0x0 [0])
        UVM_ERROR @    969666 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfa5ea5 [111110100101111010100101] vs 0x0 [0])
        UVM_ERROR @   1012666 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb5f9 [1011010111111001] vs 0x0 [0])
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 18.spi_device_flash_mode_ignore_cmds.96257944925655267385713595367308437399411291465803634993349790972602992706655
      Line 107, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 29.spi_device_flash_mode_ignore_cmds.47923506940777785105005297383616528325452121173675500835671928049346301414483
      Line 75, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 3451903391 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x0) != exp '{'{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}}
        UVM_ERROR @ 3452148287 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x0) != exp '{'{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}}
        UVM_ERROR @ 4043072131 ps: (spi_device_scoreboard.sv:1055) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 0 (1 [0x1] vs 0 [0x0])
        UVM_ERROR @ 4043980287 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x0) != exp '{'{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}}
        UVM_ERROR @ 4044735383 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x0) != exp '{'{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}, '{other_status:'h0, wel:'h0, busy:'h1}}
      

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 35.spi_device_flash_mode_ignore_cmds.54216650895166000994637541204509040227329310014922936473962861439999140756313
      Line 83, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 2021785340 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0x850530
        tl_ul_fuzzy_flash_status_q[i] = 0x12dc40
        tl_ul_fuzzy_flash_status_q[i] = 0x12dc40
        tl_ul_fuzzy_flash_status_q[i] = 0x12dc40