SPI_HOST Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.017m	6.872ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	133.732us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	185.199us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	614.734us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	35.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	86.191us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	185.199us	20	20	100.00
		spi_host_csr_aliasing	2.000s	35.313us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	20.855us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	41.465us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	62.764us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	20.000s	1.651ms	50	50	100.00
		spi_host_error_cmd	2.000s	47.985us	50	50	100.00
		spi_host_event	13.983m	86.501ms	50	50	100.00
V2	clock_rate	spi_host_speed	7.000s	10.210ms	49	50	98.00
V2	speed	spi_host_speed	7.000s	10.210ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	7.000s	10.210ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	53.000s	1.567ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	27.932us	50	50	100.00
V2	cpol_cpha	spi_host_speed	7.000s	10.210ms	49	50	98.00
V2	full_cycle	spi_host_speed	7.000s	10.210ms	49	50	98.00
V2	duplex	spi_host_smoke	2.017m	6.872ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.017m	6.872ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.783m	26.653ms	49	50	98.00
V2	spien	spi_host_spien	5.467m	18.943ms	50	50	100.00
V2	stall	spi_host_status_stall	7.967m	1.000s	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	22.000s	2.412ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	20.000s	1.651ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	41.297us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	28.930us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	117.269us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	117.269us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	133.732us	5	5	100.00
		spi_host_csr_rw	2.000s	185.199us	20	20	100.00
		spi_host_csr_aliasing	2.000s	35.313us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	38.174us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	133.732us	5	5	100.00
		spi_host_csr_rw	2.000s	185.199us	20	20	100.00
		spi_host_csr_aliasing	2.000s	35.313us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	38.174us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	293.956us	20	20	100.00
		spi_host_sec_cm	2.000s	254.576us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	293.956us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.567m	42.464ms	10	10	100.00
		TOTAL			836	840	99.52

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 2 failures:

  • Test spi_host_stress_all has 1 failures.

    • 22.spi_host_stress_all.68564927802880001522111102337384387283752609557384774450335892217822672489746
      Line 399, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 26653110343 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0xfd1da214, Comparison=CompareOpEq, exp_data=0x0, call_count=91
        UVM_INFO @ 26653110343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_status_stall has 1 failures.

    • 43.spi_host_status_stall.1144662808913565872962830534525575944198113743368760399025231385983444157552
      Line 937, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 50222516670 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0x32f701d4, Comparison=CompareOpEq, exp_data=0x0, call_count=290
        UVM_INFO @ 50222516670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 10.spi_host_speed.100449154368659230107969528812913625026941633253041470540318118905037353968098
      Line 310, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/10.spi_host_speed/latest/run.log

        UVM_FATAL @ 10210437834 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x409eb1d4, Comparison=CompareOpEq, exp_data=0x0, call_count=63
        UVM_INFO @ 10210437834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 19.spi_host_status_stall.26429033052674652787540876322808467928266650552923936748963625014357116334816
      Line 4535, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---