SRAM_CTRL/MAIN Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.243m	1.271ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.000s	29.512us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.100s	20.913us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.700s	174.538us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.090s	63.827us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.310s	1.483ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.100s	20.913us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	63.827us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.518m	128.344ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.709m	21.713ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	24.991m	142.667ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.774m	24.981ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.114m	661.872ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.687m	20.264ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.111m	16.661ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.470m	204.170ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.909m	6.903ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.422m	27.205ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.734m	3.050ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.542m	1.983ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.987m	18.258ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.128m	18.153ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.190s	2.115ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.654h	338.640ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	22.301us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.120s	138.514us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.120s	138.514us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.000s	29.512us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	20.913us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	63.827us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.230s	35.586us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.000s	29.512us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	20.913us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	63.827us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.230s	35.586us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.539m	141.227ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.190s	15.701us	0	5	0.00
		sram_ctrl_tl_intg_err	3.750s	2.582ms	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.190s	15.701us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.750s	2.582ms	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.128m	18.153ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.128m	18.153ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.100s	20.913us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.470m	204.170ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.470m	204.170ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.470m	204.170ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.111m	16.661ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	14.270s	13.237ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.539m	141.227ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.480s	13.144ms	41	50	82.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.243m	1.271ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.243m	1.271ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.470m	204.170ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.190s	15.701us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.111m	16.661ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.190s	15.701us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.190s	15.701us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.243m	1.271ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.190s	15.701us	0	5	0.00
V2S		TOTAL			125	145	86.21
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.097m	3.505ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1170	1190	98.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 9 failures:

  • Test sram_ctrl_readback_err has 9 failures.

    • 0.sram_ctrl_readback_err.40581459182892142791283716906830415997034027174136263956124435472022356403218
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1317819528 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x12) != exp (0x20)
        UVM_INFO @ 1317819528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.58585030266886914988783487339108894253628264106417012402710518104839613529345
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2464680840 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x5e)
        UVM_INFO @ 2464680840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 9.sram_ctrl_mubi_enc_err.27645763505913500158541224386903481075135878504476777906810024196977557256135
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2664063220 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2664063220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 22.sram_ctrl_mubi_enc_err.112728594012651238986324737382633319184437034361865638817586304198450702713274
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/22.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 5094415377 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 5094415377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.80703381730916587605266097966948727780555731891142540893426799520407429926418
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  20575201 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  20575201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.107612199680805705681742758129686599156458250947212442192498836484188702125445
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  15700591 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  15700591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 2.sram_ctrl_sec_cm.1463000948711112025511075542428171888057105123299289987675487286337168355918
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4008558 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4008558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.57851864399007061651241283884367190153508821544579651849537883457073063973638
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  13672483 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  13672483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_tl_intg_err has 1 failures.

    • 7.sram_ctrl_tl_intg_err.56757737055901556805769311743352721003792046031194894783445707922729368052204
      Line 360, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 249526918 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 249526918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---