SRAM_CTRL/RET Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.850m	763.387us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.970s	58.675us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.040s	36.463us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.160s	157.070us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.090s	46.164us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.120s	519.567us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.040s	36.463us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	46.164us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.240s	2.296ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.000s	1.393ms	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	23.796m	11.688ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.674m	4.539ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.591m	11.241ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.848m	3.511ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.060s	939.610us	50	50	100.00
V2	executable	sram_ctrl_executable	21.671m	15.200ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.801m	782.464us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.009m	438.822ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.767m	137.744us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.878m	507.484us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.840m	560.771us	50	50	100.00
V2	regwen	sram_ctrl_regwen	17.670m	16.097ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.250s	31.787us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.015h	52.466ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.090s	166.257us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.230s	1.892ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.230s	1.892ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.970s	58.675us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	36.463us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	46.164us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	273.679us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.970s	58.675us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	36.463us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	46.164us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	273.679us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.110s	1.572ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.050s	21.536us	0	5	0.00
		sram_ctrl_tl_intg_err	3.170s	689.662us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.050s	21.536us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.170s	689.662us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	17.670m	16.097ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	17.670m	16.097ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.040s	36.463us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.671m	15.200ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.671m	15.200ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.671m	15.200ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.060s	939.610us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.650s	168.372us	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.110s	1.572ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.650s	109.254us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.850m	763.387us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.850m	763.387us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.671m	15.200ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.050s	21.536us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.060s	939.610us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.050s	21.536us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.050s	21.536us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.850m	763.387us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.050s	21.536us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.300m	5.470ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1163	1190	97.73

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:

  • Test sram_ctrl_readback_err has 11 failures.

    • 6.sram_ctrl_readback_err.34428494896725416151337941079508800103099342958127719335330535466887390387261
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 105729277 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x77)
        UVM_INFO @ 105729277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_readback_err.10426988301937017147532020008436395041186390087304797451223037784526270808868
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  24810863 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x2d)
        UVM_INFO @  24810863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 8 failures:

  • Test sram_ctrl_mubi_enc_err has 8 failures.

    • 1.sram_ctrl_mubi_enc_err.19155930496717200567958159714727822312794136914529792132520273882523956338812
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  91710651 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  91710651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.sram_ctrl_mubi_enc_err.33509141116545277865651292856743774676012562537135685304264148096565733755041
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 117319085 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 117319085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.55318107564067416040094604193253088559664743899707706003770945281481680074661
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  19330981 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  19330981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.16547563322160141600843371978461194588427645251778310237905726512187712582217
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  21535593 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  21535593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.87567849789860125953338165783298776435408320280696625236811854918503577890544
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2275761 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2275761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.92505102125697478167594573251972210330499537663726253235356400715496041052186
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4283366ps failed at 4283366ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   8012563 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8012563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.25157118799738986355788991445141024120667823414253166953200441167623176339503
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2880803 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2880803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 4.sram_ctrl_csr_mem_rw_with_rand_reset.75756788478850421417413415666545095310769122017618685733900969453986945799871
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 388785911 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
        UVM_INFO @ 388785911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 15.sram_ctrl_csr_mem_rw_with_rand_reset.18866130420736211813741863336670967979718873532011052262956438598984908151184
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  97603957 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  97603957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 16.sram_ctrl_csr_mem_rw_with_rand_reset.93123867548681431099565605822246126626905873528898366520589700044144892956652
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 133220085 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @ 133220085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---