CHIP Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	7.092m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	7.092m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	6.417m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	7.704m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	6.523m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.978m	275.830us	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.978m	275.830us	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.978m	275.830us	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.160s	10.120us	0	3	0.00
		chip_sw_example_manufacturer	8.808m		0	3	0.00
		chip_sw_example_concurrency	3.871m	150.361us	3	3	100.00
		chip_sw_uart_smoketest_signed	15.395s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	15.790s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	15.660s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	15.660s		0	3	0.00
V1	xbar_smoke	xbar_smoke	39.880s	75.976us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	7.362m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	55.539m	4.073ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.819m	229.200us	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.230m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.341m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.744m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	7.199m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.420s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.420s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.776m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.794m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	8.400m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	8.400m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.956m	117.037us	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.563m	117.025us	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.729m	273.050us	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	16.305s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	14.419s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.931m	773.389us	1	3	33.33
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.434m	248.755us	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	10.854m	495.598us	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	10.854m	495.598us	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	57.501s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.636m	164.289us	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.636m	164.289us	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.729m	2.271ms	5	5	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.510m	145.498us	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.833m	225.715us	3	3	100.00
		chip_sw_aes_idle	3.339m	147.228us	3	3	100.00
		chip_sw_hmac_enc_idle	4.266m	161.579us	3	3	100.00
		chip_sw_kmac_idle	3.614m	144.994us	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.929m	165.648us	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	3.807m	165.664us	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	4.177m	165.712us	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	3.597m	165.680us	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	20.540s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.052s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.322s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.851s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.230s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.401s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	20.540s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.052s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.322s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.851s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.230s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.401s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	51.490s	10.260us	0	3	0.00
		chip_sw_aes_enc_jitter_en	42.650s	10.100us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	54.460s	10.120us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.920s	10.200us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.140s	10.320us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.707s		0	3	0.00
		chip_sw_clkmgr_jitter	3.371m	141.856us	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	7.959m	1.780ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.008m	10.300us	0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	52.440s	10.180us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	59.860s	10.200us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	56.590s	10.240us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	53.740s	10.220us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.103m	10.100us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.956s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	14.472s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	17.372s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	15.548s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	25.710m	905.847us	0	100	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.207m	500.121us	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.636m	164.289us	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	29.190s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.207m	500.121us	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.759s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.387s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	1.373m		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.630s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	26.951s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	25.710m	905.847us	0	100	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.729m	273.050us	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	8.035m	375.280us	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.212m	267.332us	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.200m	290.198us	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.863m	144.102us	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	25.710m	905.847us	0	100	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	25.265s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.862s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	25.710m	905.847us	0	100	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.919s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.200m	290.198us	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.317s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	22.067s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	15.431s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.476s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.878s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	15.645s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.862s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.770m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.568m	268.351us	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.391m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	3.086m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	2.301m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.952m		0	3	0.00
		chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	6.146m	268.255us	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	20.702m	1.275ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	14.400s		0	3	0.00
		chip_prim_tl_access	13.415m	1.209ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	20.540s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.052s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.322s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.851s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.230s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.401s		0	3	0.00
		chip_rv_dm_lc_disabled	9.931m	773.389us	1	3	33.33
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.168m	157.160us	3	3	100.00
		chip_sw_aes_enc_jitter_en	42.650s	10.100us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.864m	145.878us	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.339m	147.228us	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.066m	156.381us	3	3	100.00
		chip_sw_hmac_enc_jitter_en	54.460s	10.120us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.266m	161.579us	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.573m	148.982us	3	3	100.00
		chip_sw_kmac_mode_kmac	4.523m	172.142us	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	52.140s	10.320us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.146m	268.255us	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	46.500s	10.340us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.303m	204.847us	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.614m	144.994us	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	8.050m	285.082us	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	8.050m	285.082us	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	21.045s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.095m	156.808us	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.583s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.146m	268.255us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.920s	10.200us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.111h	1.469ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.490s	10.260us	0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.833m	225.715us	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.833m	225.715us	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.833m	225.715us	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.124m	264.495us	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	20.702m	1.275ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	20.702m	1.275ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.407m	313.941us	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.707s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.400s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	25.710m	905.847us	0	100	0.00
		chip_sw_data_integrity_escalation	8.400m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.124m	264.495us	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	6.146m	268.255us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	7.407m	313.941us	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.708m	154.715us	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.124m	264.495us	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	6.146m	268.255us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	7.407m	313.941us	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.708m	154.715us	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.116s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.770m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.391m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	3.086m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	2.301m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.952m		0	3	0.00
		chip_sw_lc_ctrl_transition	24.483s		0	15	0.00
		chip_prim_tl_access	13.415m	1.209ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	13.415m	1.209ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	1.147m		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	18.666s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	14.472s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	51.490s	10.260us	0	3	0.00
		chip_sw_aes_enc_jitter_en	42.650s	10.100us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	54.460s	10.120us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.920s	10.200us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	52.140s	10.320us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.707s		0	3	0.00
		chip_sw_clkmgr_jitter	3.371m	141.856us	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	3.809m	137.296us	0	3	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	3.809m	137.296us	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.090m	138.787us	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.034m	136.497us	0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.734m	251.562us	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.740m	192.451us	2	3	66.67
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.990m	164.735us	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.708m	154.715us	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	8.035m	375.280us	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	8.035m	375.280us	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.921m	157.116us	3	3	100.00
		chip_sw_aon_timer_smoketest	4.237m	163.216us	3	3	100.00
		chip_sw_clkmgr_smoketest	4.012m	142.938us	3	3	100.00
		chip_sw_csrng_smoketest	3.731m	144.800us	3	3	100.00
		chip_sw_gpio_smoketest	4.372m	165.822us	3	3	100.00
		chip_sw_hmac_smoketest	4.859m	182.050us	3	3	100.00
		chip_sw_kmac_smoketest	4.596m	171.113us	3	3	100.00
		chip_sw_otbn_smoketest	5.854m	216.114us	3	3	100.00
		chip_sw_otp_ctrl_smoketest	3.482m	148.068us	3	3	100.00
		chip_sw_rv_plic_smoketest	4.304m	145.079us	3	3	100.00
		chip_sw_rv_timer_smoketest	5.352m	248.751us	3	3	100.00
		chip_sw_rstmgr_smoketest	3.651m	141.677us	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.868m	145.484us	3	3	100.00
		chip_sw_uart_smoketest	3.998m	155.825us	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	1.190m		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	15.395s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	7.362m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.424s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.146m	195.339us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.159m	232.859us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.912m	225.499us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.479m	196.508us	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.034s		0	3	0.00
		chip_rv_dm_lc_disabled	9.931m	773.389us	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.748s		0	3	0.00
		chip_sw_lc_walkthrough_prod	15.420s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	16.272s		0	3	0.00
		chip_sw_lc_walkthrough_rma	37.959s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	23.034s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	9.838m	584.533us	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.328m	690.500us	3	3	100.00
		rom_volatile_raw_unlock	13.571s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	34.146s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	6.597m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	6.881m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	4.065m	200.361us	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	4.065m	200.361us	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	15.660s		0	3	0.00
		chip_same_csr_outstanding	15.060s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	15.660s		0	3	0.00
		chip_same_csr_outstanding	15.060s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.809m	602.659us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.660s	13.498us	100	100	100.00
		xbar_smoke_large_delays	9.939m	2.842ms	100	100	100.00
		xbar_smoke_slow_rsp	11.354m	2.278ms	100	100	100.00
		xbar_random_zero_delays	2.262m	78.665us	100	100	100.00
		xbar_random_large_delays	37.448m	12.552ms	100	100	100.00
		xbar_random_slow_rsp	55.303m	12.543ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.796m	216.198us	100	100	100.00
		xbar_error_and_unmapped_addr	2.562m	203.494us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	5.546m	524.596us	100	100	100.00
		xbar_error_and_unmapped_addr	2.562m	203.494us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.917m	932.297us	100	100	100.00
		xbar_access_same_device_slow_rsp	59.170m	13.218ms	76	100	76.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.957m	411.689us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	32.526m	4.048ms	100	100	100.00
		xbar_stress_all_with_error	31.143m	3.531ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	57.557m	5.214ms	95	100	95.00
		xbar_stress_all_with_reset_error	49.741m	5.407ms	98	100	98.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.993s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	15.171s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	15.111s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.977s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.637s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.621s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.415s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	15.463s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	14.928s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.324s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.461s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	15.024s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	24.092s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	56.212s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	48.045s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	51.691s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	54.361s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.075m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.343m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	47.319s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.218m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.045m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	50.829s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	56.338s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	57.521s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	50.541s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	44.974s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	41.166s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	22.820s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.504s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.500s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.394s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.374s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	14.985s		0	3	0.00
		rom_e2e_asm_init_dev	15.409s		0	3	0.00
		rom_e2e_asm_init_prod	14.409s		0	3	0.00
		rom_e2e_asm_init_prod_end	16.118s		0	3	0.00
		rom_e2e_asm_init_rma	14.431s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	15.334s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	15.865s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	15.174s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	14.056s		0	3	0.00
V2		TOTAL			1815	2426	74.81
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.596m	173.724us	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.508m	136.560us	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.195s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.712s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.242s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	15.145s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	25.710m	905.847us	0	100	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.109m		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.058m	158.236us	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	18.727s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.792s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.195s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.712s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.242s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	14.357s		0	1	0.00
		rom_e2e_jtag_inject_dev	13.841s		0	1	0.00
		rom_e2e_jtag_inject_rma	13.574s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.284s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	24.158m	905.615us	0	3	0.00
		chip_sw_entropy_src_kat_test	3.847m	144.273us	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	3.657m	141.572us	3	3	100.00
		chip_plic_all_irqs_0	10.237m	346.711us	3	3	100.00
		chip_plic_all_irqs_10	9.248m	302.015us	3	3	100.00
		chip_sw_dma_inline_hashing	4.594m	188.596us	3	3	100.00
		chip_sw_dma_abort	4.206m	180.936us	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	15.622s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	14.875s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	13.395s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	14.131s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	14.909s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	15.377s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	13.976s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	14.437s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	15.121s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	22.587s		0	3	0.00
		chip_sw_entropy_src_smoketest	4.461m	171.769us	3	3	100.00
		chip_sw_mbx_smoketest	10.007m	445.680us	3	3	100.00
		TOTAL			1948	2665	73.10

Failure Buckets

• Job returned non-zero exit code has 437 failures:

  • Test chip_sw_example_manufacturer has 3 failures.

    • 0.chip_sw_example_manufacturer.81477280402032370285505617178084804037806396786834305729405334977338153364471
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

        Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 510.376s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_example_manufacturer.69070958530123632437768716433491952133484514604679426650229287137737475754593
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

        Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 42.651s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_data_integrity_escalation has 6 failures.

    • 0.chip_sw_data_integrity_escalation.56934316885577803518187161425283813325815176725710903771519235572237582364380
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 491.782s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_data_integrity_escalation.80639158765297282924494652907816708318382347041733946113978410174030591856724
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 17.782s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 4 more failures.

  • Test chip_sw_sleep_pin_wake has 3 failures.

    • 0.chip_sw_sleep_pin_wake.5065366215414177491887340792494110378959405960824743409237651314803065608387
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 451.207s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_sleep_pin_wake.106536142890025914173161490012666345976223052569205539371199085497062967644602
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 23.730s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_sleep_pin_retention has 3 failures.

    • 0.chip_sw_sleep_pin_retention.92411510392664582741114089020395429963418350433924244298246746911026211235948
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 452.815s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_sleep_pin_retention.31543909808606738066404644893469803818880069505496543001242058288221920330538
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 1.791s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_uart_tx_rx has 5 failures.

    • 0.chip_sw_uart_tx_rx.32454316188700795285870664671574701956805468935020463224609078682366835135787
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

        Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 410.827s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_uart_tx_rx.78551971600556983640777219295387215107412297805370031782216468245434070035466
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

        Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 10.215s, Critical Path: 0.00s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 3 more failures.

  • ... and 125 more tests.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 91 failures:

  • Test chip_sw_all_escalation_resets has 88 failures.

    • 0.chip_sw_all_escalation_resets.71290068017825425395649660799832971915344012142199417470425783659396542494105
      Line 545, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 905.862000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.862000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_all_escalation_resets.86374468939492036314237158814588586953754215038780446187137096766251331970146
      Line 459, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 905.751000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.751000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 86 more failures.

  • Test chip_sw_rstmgr_rst_cnsty_escalation has 3 failures.

    • 0.chip_sw_rstmgr_rst_cnsty_escalation.103408575504791999668095114727500984078298146839516881583188598920335860583676
      Line 528, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

        UVM_ERROR @ 905.814000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.814000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_rst_cnsty_escalation.58452584398702510548419310489403500287260705868115061292420555963688764674078
      Line 464, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

        UVM_ERROR @ 905.859000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 905.859000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 33 failures:

  • Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 3 failures.

    • 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.91716731192359193099070793454894249363520641604682024014555411921116004737236
      Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.40810207298847467881398328156582385881397553914462556400666551105044528663122
      Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aes_enc_jitter_en has 3 failures.

    • 0.chip_sw_aes_enc_jitter_en.35063854219644972944413533598119261818703894774092561999914193966188707207726
      Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aes_enc_jitter_en.13740131903017902016141752612103891583055339778201248410659070287428137882869
      Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_hmac_enc_jitter_en has 3 failures.

    • 0.chip_sw_hmac_enc_jitter_en.107695489115555853629126642494472922436125836682215511396466654204894095342436
      Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_hmac_enc_jitter_en.102601145718646953493738306562400948025500678317415637474833872068109356061710
      Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.102457069211706208956004763255066058288393687692247172954104646052469670537042
      Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.1374464959044084532034217123886593142572679129132750309674418823338885114508
      Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.

    • 0.chip_sw_kmac_mode_kmac_jitter_en.61531262647779036052564538603157571670020993522589012842739881136254388553395
      Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_kmac_mode_kmac_jitter_en.23798284496887736221978038348451456901837035949825420698073454469139655542540
      Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • ... and 6 more tests.

• Job timed out after * minutes has 31 failures:

  • Test xbar_access_same_device_slow_rsp has 24 failures.

    • 8.xbar_access_same_device_slow_rsp.113801853012546877696179093284243319546585252143446100116650086711374574664851
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log

        Job timed out after 60 minutes
      

    • 10.xbar_access_same_device_slow_rsp.73046011444369970743072501343773615792557317036729408344383828535544858906649
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 22 more failures.

  • Test xbar_stress_all_with_rand_reset has 5 failures.

    • 16.xbar_stress_all_with_rand_reset.6275024424948494358580748627133108451573362109526935305706599743536629688926
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/run.log

        Job timed out after 60 minutes
      

    • 64.xbar_stress_all_with_rand_reset.70514332938601457552938352527817648691948733289151864679712135565877327214935
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 3 more failures.

  • Test xbar_stress_all_with_reset_error has 2 failures.

    • 19.xbar_stress_all_with_reset_error.99080239504821838950713795630134077706919932777843950219629834754849307876237
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log

        Job timed out after 60 minutes
      

    • 53.xbar_stress_all_with_reset_error.84596504434266899410015001229718486382688586686721839206028371360842662692912
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/53.xbar_stress_all_with_reset_error/latest/run.log

        Job timed out after 60 minutes
      

• Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 30 failures:

  • Test chip_tl_errors has 30 failures.

    • 0.chip_tl_errors.61642018072944495419312840579717863097921982020366608309106984797763121582841
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 118.009000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 118.009000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_tl_errors.54097808222354693007326730130956143367390206716526438648119829980909034470095
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 118.148000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 118.148000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 28 more failures.

• Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 16 failures:

  • Test chip_sw_rstmgr_cpu_info has 3 failures.

    • 0.chip_sw_rstmgr_cpu_info.67608816053330539952931904595331597061819743294058623910029253235064703280140
      Line 539, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 375.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 375.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_cpu_info.109826854520288210347398996923810275919676110216030837989199519391618863146582
      Line 487, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 375.312000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 375.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_aes_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_aes_trans.94213257688718712474633316333203882971176461332458240800896649559876103281320
      Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_aes_trans.110738339091774131585289024577195408954964262197162324198155615583111555751960
      Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.696000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_hmac_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_hmac_trans.75154960767438114182474825559399496875276985027842145124839450981290408155085
      Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_hmac_trans.92284581702173012780890106132955180958126244904126915173487531005495797494365
      Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.632000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.632000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_kmac_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_kmac_trans.96791642188489413052963846208760294207607320196626122556266696790624812997771
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.584000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.584000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_kmac_trans.41996580820827313218442969521274292390109286731490143595703840038581742268972
      Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.712000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.712000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_otbn_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_otbn_trans.26375056084298985493504870795595244020776755548499050264625439733974162686906
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_otbn_trans.39189075818400422740660745724791943453548072088318082289678713705950084335038
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

            Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
        UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
        UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • ... and 1 more tests.

• Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:

  • Test chip_padctrl_attributes has 10 failures.

    • 0.chip_padctrl_attributes.53729593663022397537338357348822064243542661070779823018084416616164247708419
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • 1.chip_padctrl_attributes.115313403867859086713302984261148299747334590501928908166782403853198666983064
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • ... and 8 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.71409543241625642046006105528083827943061914909963468611345798447189512976937
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_bit_bash.8217988076380371826174979252771448138731462047290601420480860975115196952417
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.108453727602249947478375618533959327391244893376598863990466469204986130661379
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_aliasing.111509236536422289511610451602789406597137129471938043262038534835701493069248
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.50143362361805099370471634308008612242964803046013569713480314089173778730836
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_same_csr_outstanding.45028615739018414059118599594114194453897605325060790655929269693261311556829
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:

  • Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation.85910566994306968240420675775479332476207388255888017668434154410688679527001
      Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 268.255000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1093877289330117245603074575264444677479829582814283969554534762667596761726676512745974732722718334925355175656538207274061952588971860946432765228047452 [0x14e2c2c4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd392b472357f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.255000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation.76070340917868283181909690397704593939628662044418312888852868870340630230559
      Line 439, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 268.320000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (485362711223367676240282908885881848279345833331920658844859461603361304615319783758258857099084482063246799964503361126894538723750414133234428532841564 [0x944674caae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd38f12d7bd7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_prod.56318899458268994998896150045087030391111596742911805808080122379204335709184
      Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 268.060000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6882395678193550974322237481466101330583968409103204303935976496894423571605052628006976145644102522068643880713829028947570710057151192078581309179780188 [0x83687306aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3053ec3f77f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 268.060000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation_prod.98191917580274278537134900107932082051738491733681118166975041721491533508399
      Line 461, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 267.999000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1706046432908002190435307818506384540817960795421704166026126710742169489399870457924218064787086362898134717736028916750950490727859125763210023073569884 [0x2092fb33aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a6c44bc27f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 267.999000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

  • Test chip_jtag_csr_rw has 3 failures.

    • 0.chip_jtag_csr_rw.46657989578538351815344599984047530326097403207160840952713143977640107657591
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 117.028000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'hae065e0e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h0  a_user: 'h26969  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.028000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_csr_rw.65800569320580265689462778804126641525248255608761664284439337925400860007319
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 117.005000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'h48a38d6f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h0  a_user: 'h26954  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.005000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_jtag_mem_access has 3 failures.

    • 0.chip_jtag_mem_access.100258183785826836898607393027346476557473024653645223753071008676204711229475
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 117.040000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'h4cc55cbf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h0  a_user: 'h26920  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.040000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_mem_access.72477239905120598053518343635921390156607340115681221025909627459209681568385
      Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 117.028000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42095) { a_addr: 'h30480000  a_data: 'h7f164ef6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h1  a_user: 'h24881  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 117.028000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 5 failures:

  • Test chip_sw_otp_ctrl_escalation has 1 failures.

    • 0.chip_sw_otp_ctrl_escalation.95731056785935784328317530909474191105075799784586675323084598364980148913350
      Line 444, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 158.236000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 158.236000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_all_escalation_resets has 4 failures.

    • 9.chip_sw_all_escalation_resets.38495872652537462197298529549707752599807323167722539730704557921501106249237
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 158.100000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 158.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 65.chip_sw_all_escalation_resets.64153677514179376572707844238167795174517681869317851101566008201986347056271
      Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 158.064000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 158.064000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test chip_sw_example_rom has 3 failures.

    • 0.chip_sw_example_rom.30095957026299835696049329961525118746103058829402386582075809021513451476390
      Line 1222, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_example_rom.62205419390914400686366448789440776063783061645577550564112812170118711585155
      Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:

  • Test chip_sw_spi_device_pass_through_collision has 3 failures.

    • 0.chip_sw_spi_device_pass_through_collision.13144924551232891940081841884336681275804922641758329512138165585028187193123
      Line 474, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 172.599000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 172.599000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_spi_device_pass_through_collision.106887035980720589558244143708449428364015570334716380400445534164883060792999
      Line 456, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 181.968000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 181.968000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 3 failures:

  • Test chip_sw_rstmgr_alert_info has 3 failures.

    • 0.chip_sw_rstmgr_alert_info.44726971056788632640893954421464395101544537661758295445549418867912701712082
      Line 548, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 290.198000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 290.198000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_alert_info.53543437293028464835391990037046039019858509389175428297032850643221316920808
      Line 470, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 290.074000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
        UVM_INFO @ 290.074000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:

  • Test chip_sw_soc_proxy_external_wakeup has 3 failures.

    • 0.chip_sw_soc_proxy_external_wakeup.74711694446134184734803225432202409404275088372388011387499942635781028769456
      Line 482, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 138.787000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 138.787000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_external_wakeup.28659674791666857598499098959182197140345746704835049975012305805234116801723
      Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 138.784000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 138.784000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 3 failures:

  • Test chip_sw_soc_proxy_gpios has 3 failures.

    • 0.chip_sw_soc_proxy_gpios.104954342021446842452022193168015289907114641846959337295814755453636041188931
      Line 486, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log

        UVM_ERROR @ 136.417000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
        UVM_INFO @ 136.417000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_gpios.1306232518880887933330083868832123270417891214462276082471192443225278364048
      Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log

        UVM_ERROR @ 136.497000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
        UVM_INFO @ 136.497000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 3 failures:

  • Test chip_sw_aon_timer_irq has 3 failures.

    • 0.chip_sw_aon_timer_irq.5333881172024137946505043298655041055132656205090976399425617365082779197177
      Line 494, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 540.533000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3991 usec which is not in the range 364 usec and 417 usec
        UVM_INFO @ 540.533000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_irq.66273005432825418675058943356039488758690552116171989624987166721692017702853
      Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 495.598000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3522 usec which is not in the range 322 usec and 369 usec
        UVM_INFO @ 495.598000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:

  • Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.

    • 0.chip_sw_aon_timer_wdog_bite_reset.47401827459217578682175910658758348749174317455128932923087482476501906172246
      Line 499, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 164.320000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 164.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_wdog_bite_reset.112701440954061765946294719339635146884959879971729631570272918662311699763788
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 164.292000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 164.292000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:

  • Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.

    • 0.chip_sw_rv_core_ibex_nmi_irq.60175401627003773305525187341317612484617541217934135846278241986957493321318
      Line 481, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 251.562000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 251.562000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rv_core_ibex_nmi_irq.33906291751505811077557462559933688543960469206707867130972580706175630438571
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 251.575000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 251.575000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:

  • Test chip_sw_kmac_app_rom has 3 failures.

    • 0.chip_sw_kmac_app_rom.72007696718641361300443075159934896597147268345914006615348293058034894994956
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_kmac_app_rom.92157910024886083389040699599819338787609938406842281658307188964139464718895
      Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 5.chip_sw_all_escalation_resets.95599355279978295652880993043699102494233790430846140276231350256382453577554
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.120001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 30.chip_sw_all_escalation_resets.76165119104412776200955237765078208462430887986536798215301319077801239350934
      Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.340001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 48.chip_sw_all_escalation_resets.26053151542961320465623557681110008757161940494436587726872084528783776862666
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 158.821000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 158.821000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 77.chip_sw_all_escalation_resets.34214011065163581450658555360087085716002052955212063649547803468561353208741
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 158.884000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 158.884000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 2 failures:

  • Test chip_sw_soc_proxy_smoketest has 2 failures.

    • 0.chip_sw_soc_proxy_smoketest.73194844669440565511694470230940614386023025996915824388046132709871908972011
      Line 516, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log

        UVM_ERROR @ 137.296000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
        UVM_INFO @ 137.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_smoketest.4442371491619151677474554007397876575408705985797189115091138113305288555949
      Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log

        UVM_ERROR @ 137.296000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
        UVM_INFO @ 137.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

  • Test chip_rv_dm_lc_disabled has 2 failures.

    • 0.chip_rv_dm_lc_disabled.48815868010005598001474849709520319659882148710621936886735693340793331356700
      Line 224, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 253.788000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40724 read out mismatch
        UVM_INFO @ 253.788000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_rv_dm_lc_disabled.65670957013476747179172514505048265817458179332034682537715896019608876767423
      Line 216, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 130.307000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40700 read out mismatch
        UVM_INFO @ 130.307000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 2 failures:

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 1.chip_sw_all_escalation_resets.63930717766246358970962715439717639860636311413555642084328213979461754889751
      Line 475, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 160.244000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 160.244000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 75.chip_sw_all_escalation_resets.114380632493115098100967967706578265261315541822642281655853016711207718000248
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 160.236000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 160.236000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:

  • Test chip_sw_rv_core_ibex_rnd has 1 failures.

    • 0.chip_sw_rv_core_ibex_rnd.9276007320584523915630507494233439525607421430792517687290193076460665267065
      Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log

        UVM_ERROR @ 155.479000 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
        UVM_INFO @ 155.479000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 1 failures:

  • Test chip_sw_dma_abort has 1 failures.

    • 0.chip_sw_dma_abort.20924471222461973217743077624122224785542753314365631663323241231711563184824
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

        UVM_ERROR @ 192.947000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
        UVM_INFO @ 192.947000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 1 failures:

  • Test chip_sw_dma_abort has 1 failures.

    • 1.chip_sw_dma_abort.79201895629841499261800614315298669785491641113419089564807802047532678586510
      Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

        UVM_ERROR @ 180.936000 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
        UVM_INFO @ 180.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

  • Test chip_sw_dma_abort has 1 failures.

    • 2.chip_sw_dma_abort.111886960095227789611186261249506330377296279613996438133855407300237049690502
      Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 155.776000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 155.776000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---