AES/UNMASKED Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: `53b5e04`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	92.963us	2	2	100.00
V1	smoke	aes_smoke	13.000s	1645.015us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	92.358us	10	10	100.00
V1	csr_rw	aes_csr_rw	6.000s	86.383us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1034.572us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	168.879us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	129.603us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	86.383us	40	40	100.00
		aes_csr_aliasing	7.000s	168.879us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	13.000s	1645.015us	100	100	100.00
		aes_config_error	16.000s	689.282us	100	100	100.00
		aes_stress	14.000s	677.711us	100	100	100.00
V2	key_length	aes_smoke	13.000s	1645.015us	100	100	100.00
		aes_config_error	16.000s	689.282us	100	100	100.00
		aes_stress	14.000s	677.711us	100	100	100.00
V2	back2back	aes_stress	14.000s	677.711us	100	100	100.00
		aes_b2b	43.000s	1000.277us	100	100	100.00
V2	backpressure	aes_stress	14.000s	677.711us	100	100	100.00
V2	multi_message	aes_smoke	13.000s	1645.015us	100	100	100.00
		aes_config_error	16.000s	689.282us	100	100	100.00
		aes_stress	14.000s	677.711us	100	100	100.00
		aes_alert_reset	11.000s	793.662us	99	100	99.00
V2	failure_test	aes_man_cfg_err	4.000s	292.381us	100	100	100.00
		aes_config_error	16.000s	689.282us	100	100	100.00
		aes_alert_reset	11.000s	793.662us	99	100	99.00
V2	trigger_clear_test	aes_clear	39.000s	1823.281us	100	100	100.00
V2	nist_test_vectors	aes_nist_vectors	28.000s	2002.084us	2	2	100.00
V2	reset_recovery	aes_alert_reset	11.000s	793.662us	99	100	99.00
V2	stress	aes_stress	14.000s	677.711us	100	100	100.00
V2	sideload	aes_stress	14.000s	677.711us	100	100	100.00
		aes_sideload	6.000s	631.298us	100	100	100.00
V2	deinitialization	aes_deinit	10.000s	669.379us	100	100	100.00
V2	stress_all	aes_stress_all	107.000s	10074.017us	19	20	95.00
V2	alert_test	aes_alert_test	3.000s	61.918us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	315.737us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	315.737us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	92.358us	10	10	100.00
		aes_csr_rw	6.000s	86.383us	40	40	100.00
		aes_csr_aliasing	7.000s	168.879us	10	10	100.00
		aes_same_csr_outstanding	6.000s	62.803us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	92.358us	10	10	100.00
		aes_csr_rw	6.000s	86.383us	40	40	100.00
		aes_csr_aliasing	7.000s	168.879us	10	10	100.00
		aes_same_csr_outstanding	6.000s	62.803us	40	40	100.00
V2		TOTAL			1000	1002	99.80
V2S	reseeding	aes_reseed	30.000s	2221.015us	100	100	100.00
V2S	fault_inject	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	221.646us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	221.646us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	221.646us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	221.646us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	174.731us	40	40	100.00
V2S	tl_intg_err	aes_tl_intg_err	7.000s	194.196us	40	40	100.00
		aes_sec_cm	6.000s	2724.260us	10	10	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	194.196us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	793.662us	99	100	99.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	221.646us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	1645.015us	100	100	100.00
		aes_stress	14.000s	677.711us	100	100	100.00
		aes_alert_reset	11.000s	793.662us	99	100	99.00
		aes_core_fi	62.000s	10039.986us	130	140	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	221.646us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	63.564us	100	100	100.00
		aes_stress	14.000s	677.711us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	677.711us	100	100	100.00
		aes_sideload	6.000s	631.298us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	63.564us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	63.564us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	63.564us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	63.564us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	63.564us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	677.711us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	677.711us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	31.000s	1524.232us	99	100	99.00
V2S	sec_cm_main_fsm_redun	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
		aes_ctr_fi	6.000s	390.448us	99	100	99.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	31.000s	1524.232us	99	100	99.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	10014.769us	671	700	95.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	31.000s	1524.232us	99	100	99.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_ctr_fi	6.000s	390.448us	99	100	99.00
V2S	sec_cm_ctrl_sparse	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
		aes_ctr_fi	6.000s	390.448us	99	100	99.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	793.662us	99	100	99.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
		aes_ctr_fi	6.000s	390.448us	99	100	99.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
		aes_ctr_fi	6.000s	390.448us	99	100	99.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_ctr_fi	6.000s	390.448us	99	100	99.00
V2S	sec_cm_data_reg_local_esc	aes_fi	31.000s	1524.232us	99	100	99.00
		aes_control_fi	57.000s	10009.577us	576	600	96.00
		aes_cipher_fi	58.000s	10014.769us	671	700	95.86
V2S		TOTAL			1905	1970	96.70
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	33.000s	564.826us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3117	3204	97.28

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.62	94.63	98.74	92.97	98.07	91.11	97.88	97.59

Failure Buckets

Job timed out after * minutes has 21 failures:
- Test aes_cipher_fi has 8 failures.
  - 11.aes_cipher_fi.109378378774483822096286501628683985097730149164178849680078882236844765193337
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 106.aes_cipher_fi.30969083777989339824791982295742703255849260760534702096259335785854085846480
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/106.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
- Test aes_control_fi has 12 failures.
  - 20.aes_control_fi.47138229852473258033472512788314190160637414165753703094941038000087918065084
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 34.aes_control_fi.69678153324437465377094104759004419356431055612094536093289681091306715301241
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_ctr_fi has 1 failures.
  - 40.aes_ctr_fi.83638474661862995608578205777429454662098617898671953235496234348496603933433
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/40.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 20 failures:
- Test aes_cipher_fi has 20 failures.
  - 3.aes_cipher_fi.61018120763543986754038002192714197076459047412515503657420207545906501573192
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003628493 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003628493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_cipher_fi.68012165985272344098834812387321508868018465943066972117986756686520232358833
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012290457 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012290457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 12 failures:

Test aes_stress_all_with_rand_reset has 12 failures.

2.aes_stress_all_with_rand_reset.71451542246637396024024556043903924112668915827952823844877288213115688931232
Line 1009, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1124366917 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1124366917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.4142378048447386184320640510222882320525791045901383058315467523263025104724
Line 1515, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1695876650 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1695876650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 102.aes_control_fi.26158972424085239639366734554582905996389222016863004867526510343891815110234
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/102.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013601380 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013601380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 125.aes_control_fi.11838310122178812200444358896493456863577526033879225831269873609303441248197
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/125.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10099826149 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10099826149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 46.aes_core_fi.72157002007006296784510929423989098679653103645799173062169526100776356533065
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002114873 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002114873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 34.aes_core_fi.56041301762999019744918808235286434896363548759508280172679534320731617720019
    Line 148, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025730290 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025730290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.87934576441319209069607880355897442459302348351335361856208869538761768395492
    Line 1294, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1145692727 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1145692727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.aes_stress_all_with_rand_reset.55280679705863664129154306435045513722915573877843250051093673471809278395945
    Line 168, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  90428306 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  90428306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 1.aes_stress_all_with_rand_reset.88090060561985597096162482065697816979100776865154147078523907966669826292619
    Line 151, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  11015562 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  11015562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.2847657515894852373149563646648798787777457546674735410297339937614348269678
    Line 1011, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 351528867 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 351528867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 1 failures.

45.aes_alert_reset.69962690191407676246037761394475246145566104988994804024701015506446219538806
Line 3766, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/45.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 20757775 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 20737367 PS)
  UVM_ERROR @  20757775 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  20757775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

48.aes_fi.84051576046219709060458605087778110003747971346097527576084284998944523202848
Line 778, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/48.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 47038224 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 46979400 PS)
  UVM_ERROR @  47038224 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  47038224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 1.aes_core_fi.63366314880269030457739716177365140356829971112113399884733332561893714472619
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10087932235 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xf1537884, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10087932235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.25802716495056126621253264441007408927431966022006353557321722759397410078790
    Line 636242, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 10074017304 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xc56cb284, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10074017304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.56850187830045625851674679958269775016126418443198904149900990506651881018395
    Line 944, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 929079566 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 929079566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 19.aes_core_fi.101288340473753563525850041262427928460682478893196209113001454864533395536033
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030500289 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030500289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 49.aes_core_fi.93081926660929745648046498507740537510192131240347104072005091341655101821843
    Line 144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039986238 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x2317bc84, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10039986238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.28426745527471225533972125490638527053930195195612967310388392374584563473592
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10061045441 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x2bf62284, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10061045441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 93.aes_cipher_fi.14581315933345107323251646216762217910268063941204664601809021233665310207164
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.29091252782527073501618433303179272122938806391938629155614511368499581831709
    Line 539, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 748325320 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 748325320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```