CSRNG Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	33.000s	40.721us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	39.187us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	234.588us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	17.000s	453.922us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	203.672us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	309.524us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	234.588us	20	20	100.00
		csrng_csr_aliasing	7.000s	203.672us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	37.000s	190.899us	200	200	100.00
V2	alerts	csrng_alert	57.000s	5081.288us	500	500	100.00
V2	err	csrng_err	33.000s	54.961us	500	500	100.00
V2	cmds	csrng_cmds	536.000s	57685.948us	50	50	100.00
V2	life cycle	csrng_cmds	536.000s	57685.948us	50	50	100.00
V2	stress_all	csrng_stress_all	1614.000s	139945.391us	47	50	94.00
V2	intr_test	csrng_intr_test	3.000s	81.687us	50	50	100.00
V2	alert_test	csrng_alert_test	33.000s	40.937us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	651.598us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	651.598us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	39.187us	5	5	100.00
		csrng_csr_rw	4.000s	234.588us	20	20	100.00
		csrng_csr_aliasing	7.000s	203.672us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	796.996us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	39.187us	5	5	100.00
		csrng_csr_rw	4.000s	234.588us	20	20	100.00
		csrng_csr_aliasing	7.000s	203.672us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	796.996us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_tl_intg_err	9.000s	621.142us	20	20	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_config_regwen	csrng_csr_rw	4.000s	234.588us	20	20	100.00
		csrng_regwen	32.000s	74.343us	50	50	100.00
V2S	sec_cm_config_mubi	csrng_alert	57.000s	5081.288us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1614.000s	139945.391us	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	57.000s	5081.288us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1614.000s	139945.391us	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	57.000s	5081.288us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	621.142us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
		csrng_sec_cm	35.000s	98.357us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	37.000s	190.899us	200	200	100.00
		csrng_err	33.000s	54.961us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	277.000s	19200.501us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1627	1630	99.82

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.62	98.79	97.03	99.91	96.83	92.08	100.00	95.53	90.01

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 12.csrng_stress_all.106788029336391710750882835531441451177039137779919252981794138293492431769029
      Line 191, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log

        UVM_ERROR @ 5072528030 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 5072528030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 24.csrng_stress_all.33661374918931185994674047057669782356943645455314236190822761601911131617363
      Line 161, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/24.csrng_stress_all/latest/run.log

        UVM_ERROR @ 9422955821 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 9422955821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.