DMA Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	350.047us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	9.000s	506.600us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	375.692us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	103.873us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	30.831us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	3741.519us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	945.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	56.127us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	30.831us	20	20	100.00
		dma_csr_aliasing	8.000s	945.980us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	113.000s	8638.156us	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	527.000s	45533.374us	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	513.000s	693541.065us	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	513.000s	693541.065us	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	527.000s	45533.374us	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	934.000s	94226.040us	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	513.000s	693541.065us	3	3	100.00
V2	dma_abort	dma_abort	17.000s	1163.962us	5	5	100.00
V2	dma_stress_all	dma_stress_all	239.000s	36948.731us	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	11.750us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	10.693us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	160.095us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	160.095us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	103.873us	5	5	100.00
		dma_csr_rw	2.000s	30.831us	20	20	100.00
		dma_csr_aliasing	8.000s	945.980us	5	5	100.00
		dma_same_csr_outstanding	3.000s	456.205us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	103.873us	5	5	100.00
		dma_csr_rw	2.000s	30.831us	20	20	100.00
		dma_csr_aliasing	8.000s	945.980us	5	5	100.00
		dma_same_csr_outstanding	3.000s	456.205us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	73.143us	5	5	100.00
		dma_generic_stress	934.000s	94226.040us	5	5	100.00
		dma_handshake_stress	513.000s	693541.065us	3	3	100.00
V2S	dma_config_lock	dma_config_lock	15.000s	1329.377us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	113.610us	20	20	100.00
		dma_sec_cm	2.000s	10.359us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	160.000s	13247.001us	25	25	100.00
		dma_longer_transfer	25.000s	4571.892us	5	5	100.00
		dma_stress_all_with_rand_reset	6.000s	210.421us	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.97	97.38	95.83	96.89	95.99	83.12	92.96	95.97	77.42

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.109172760076191031696389627880812875657815096134889804673824389679794209667450
      Line 92, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  210420976ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  210420976ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---