EDN Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.280s 16.906us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.010s 30.178us 5 5 100.00
V1 csr_rw edn_csr_rw 0.970s 13.533us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.560s 268.147us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.330s 63.842us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.480s 30.267us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.970s 13.533us 20 20 100.00
edn_csr_aliasing 1.330s 63.842us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.740s 379.603us 300 300 100.00
V2 csrng_commands edn_genbits 4.740s 379.603us 300 300 100.00
V2 genbits edn_genbits 4.740s 379.603us 300 300 100.00
V2 interrupts edn_intr 1.500s 20.322us 50 50 100.00
V2 alerts edn_alert 1.780s 215.833us 200 200 100.00
V2 errs edn_err 1.640s 30.792us 100 100 100.00
V2 disable edn_disable 1.210s 12.355us 50 50 100.00
edn_disable_auto_req_mode 1.430s 151.508us 50 50 100.00
V2 stress_all edn_stress_all 5.420s 505.779us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 14.072us 50 50 100.00
V2 alert_test edn_alert_test 2.320s 150.790us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.260s 254.260us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.260s 254.260us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.010s 30.178us 5 5 100.00
edn_csr_rw 0.970s 13.533us 20 20 100.00
edn_csr_aliasing 1.330s 63.842us 5 5 100.00
edn_same_csr_outstanding 1.330s 40.651us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.010s 30.178us 5 5 100.00
edn_csr_rw 0.970s 13.533us 20 20 100.00
edn_csr_aliasing 1.330s 63.842us 5 5 100.00
edn_same_csr_outstanding 1.330s 40.651us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 5.510s 908.203us 5 5 100.00
edn_tl_intg_err 3.040s 220.215us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.960s 65.175us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.780s 215.833us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.510s 908.203us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.510s 908.203us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.510s 908.203us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.510s 908.203us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.780s 215.833us 200 200 100.00
edn_sec_cm 5.510s 908.203us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.780s 215.833us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.040s 220.215us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 106.870s 12048.387us 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 1107 1130 97.96

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.71 98.87 94.23 97.02 93.02 96.33 97.56 92.94

Failure Buckets