HMAC Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.200s	860.628us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.330s	68.803us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.250s	36.475us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.550s	1102.046us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.550s	1186.536us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	629.060s	81655.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.250s	36.475us	20	20	100.00
		hmac_csr_aliasing	9.550s	1186.536us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	78.920s	1697.148us	10	10	100.00
V2	back_pressure	hmac_back_pressure	90.590s	6938.924us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	262.860s	24864.713us	30	30	100.00
		hmac_test_sha384_vectors	494.330s	48470.396us	75	75	100.00
		hmac_test_sha512_vectors	531.140s	62889.249us	75	75	100.00
		hmac_test_hmac256_vectors	15.230s	651.915us	50	50	100.00
		hmac_test_hmac384_vectors	15.880s	1465.336us	60	60	100.00
		hmac_test_hmac512_vectors	18.620s	1547.841us	75	75	100.00
V2	burst_wr	hmac_burst_wr	36.410s	7772.293us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	1119.310s	6474.134us	10	10	100.00
V2	error	hmac_error	116.050s	21107.822us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	115.380s	8220.701us	10	10	100.00
V2	save_and_restore	hmac_smoke	14.200s	860.628us	10	10	100.00
		hmac_long_msg	78.920s	1697.148us	10	10	100.00
		hmac_back_pressure	90.590s	6938.924us	25	25	100.00
		hmac_datapath_stress	1119.310s	6474.134us	10	10	100.00
		hmac_burst_wr	36.410s	7772.293us	50	50	100.00
		hmac_stress_all	2358.380s	20231.495us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.200s	860.628us	10	10	100.00
		hmac_long_msg	78.920s	1697.148us	10	10	100.00
		hmac_back_pressure	90.590s	6938.924us	25	25	100.00
		hmac_datapath_stress	1119.310s	6474.134us	10	10	100.00
		hmac_wipe_secret	115.380s	8220.701us	10	10	100.00
		hmac_test_sha256_vectors	262.860s	24864.713us	30	30	100.00
		hmac_test_sha384_vectors	494.330s	48470.396us	75	75	100.00
		hmac_test_sha512_vectors	531.140s	62889.249us	75	75	100.00
		hmac_test_hmac256_vectors	15.230s	651.915us	50	50	100.00
		hmac_test_hmac384_vectors	15.880s	1465.336us	60	60	100.00
		hmac_test_hmac512_vectors	18.620s	1547.841us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.200s	860.628us	10	10	100.00
		hmac_long_msg	78.920s	1697.148us	10	10	100.00
		hmac_back_pressure	90.590s	6938.924us	25	25	100.00
		hmac_datapath_stress	1119.310s	6474.134us	10	10	100.00
		hmac_burst_wr	36.410s	7772.293us	50	50	100.00
		hmac_error	116.050s	21107.822us	10	10	100.00
		hmac_wipe_secret	115.380s	8220.701us	10	10	100.00
		hmac_test_sha256_vectors	262.860s	24864.713us	30	30	100.00
		hmac_test_sha384_vectors	494.330s	48470.396us	75	75	100.00
		hmac_test_sha512_vectors	531.140s	62889.249us	75	75	100.00
		hmac_test_hmac256_vectors	15.230s	651.915us	50	50	100.00
		hmac_test_hmac384_vectors	15.880s	1465.336us	60	60	100.00
		hmac_test_hmac512_vectors	18.620s	1547.841us	75	75	100.00
		hmac_stress_all	2358.380s	20231.495us	50	50	100.00
V2	stress_all	hmac_stress_all	2358.380s	20231.495us	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	16.154us	50	50	100.00
V2	intr_test	hmac_intr_test	0.940s	130.619us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.410s	236.873us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.410s	236.873us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.330s	68.803us	5	5	100.00
		hmac_csr_rw	1.250s	36.475us	20	20	100.00
		hmac_csr_aliasing	9.550s	1186.536us	5	5	100.00
		hmac_same_csr_outstanding	2.720s	139.696us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.330s	68.803us	5	5	100.00
		hmac_csr_rw	1.250s	36.475us	20	20	100.00
		hmac_csr_aliasing	9.550s	1186.536us	5	5	100.00
		hmac_same_csr_outstanding	2.720s	139.696us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.360s	85.096us	5	5	100.00
		hmac_tl_intg_err	5.240s	280.319us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.240s	280.319us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.200s	860.628us	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.090s	236.236us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	911.760s	99256.640us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	0.900s	35.964us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.76	99.95	96.85	100.00	97.06	99.83	97.61	100.00