I2C Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 88.080s 4436.268us 50 50 100.00
V1 target_smoke i2c_target_smoke 39.250s 6045.965us 50 50 100.00
V1 csr_hw_reset i2c_csr_hw_reset 1.120s 44.648us 5 5 100.00
V1 csr_rw i2c_csr_rw 1.130s 26.619us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 4.120s 1879.939us 5 5 100.00
V1 csr_aliasing i2c_csr_aliasing 1.850s 74.400us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.470s 129.167us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 1.130s 26.619us 20 20 100.00
i2c_csr_aliasing 1.850s 74.400us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 host_error_intr i2c_host_error_intr 8.200s 1331.430us 1 50 2.00
V2 host_stress_all i2c_host_stress_all 2680.970s 46635.501us 7 50 14.00
V2 host_maxperf i2c_host_perf 2100.940s 72253.029us 50 50 100.00
V2 host_override i2c_host_override 1.060s 15.902us 50 50 100.00
V2 host_fifo_watermark i2c_host_fifo_watermark 281.380s 21432.319us 50 50 100.00
V2 host_fifo_overflow i2c_host_fifo_overflow 143.300s 10468.291us 50 50 100.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 1.720s 158.537us 50 50 100.00
i2c_host_fifo_fmt_empty 21.010s 1119.697us 50 50 100.00
i2c_host_fifo_reset_rx 12.060s 222.343us 50 50 100.00
V2 host_fifo_full i2c_host_fifo_full 167.250s 14417.442us 50 50 100.00
V2 host_timeout i2c_host_stretch_timeout 36.860s 945.232us 50 50 100.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 4.460s 960.480us 13 50 26.00
V2 target_glitch i2c_target_glitch 3.380s 2109.795us 0 2 0.00
V2 target_stress_all i2c_target_stress_all 2038.370s 76041.477us 49 50 98.00
V2 target_maxperf i2c_target_perf 6.410s 4051.607us 50 50 100.00
V2 target_fifo_empty i2c_target_stress_rd 50.100s 2585.297us 50 50 100.00
i2c_target_intr_smoke 9.770s 1768.983us 50 50 100.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 2.440s 915.520us 50 50 100.00
i2c_target_fifo_reset_tx 2.290s 542.799us 50 50 100.00
V2 target_fifo_full i2c_target_stress_wr 941.910s 60813.695us 50 50 100.00
i2c_target_stress_rd 50.100s 2585.297us 50 50 100.00
i2c_target_intr_stress_wr 258.180s 19976.856us 50 50 100.00
V2 target_timeout i2c_target_timeout 10.640s 1602.230us 50 50 100.00
V2 target_clock_stretch i2c_target_stretch 177.380s 4535.374us 43 50 86.00
V2 bad_address i2c_target_bad_addr 9.140s 7219.410us 50 50 100.00
V2 target_mode_glitch i2c_target_hrst 27.390s 10297.571us 29 50 58.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 4.070s 1620.512us 50 50 100.00
i2c_target_fifo_watermarks_tx 2.330s 725.754us 49 50 98.00
V2 host_mode_config_perf i2c_host_perf 2100.940s 72253.029us 50 50 100.00
i2c_host_perf_precise 2254.020s 24304.126us 50 50 100.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 36.860s 945.232us 50 50 100.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 11.570s 718.233us 48 50 96.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 3.880s 2185.669us 50 50 100.00
i2c_target_nack_acqfull_addr 3.490s 919.555us 50 50 100.00
i2c_target_nack_txstretch 2.170s 490.741us 31 50 62.00
V2 host_mode_halt_on_nak i2c_host_may_nack 24.530s 3708.876us 50 50 100.00
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 3.410s 462.999us 50 50 100.00
V2 alert_test i2c_alert_test 0.980s 16.352us 50 50 100.00
V2 intr_test i2c_intr_test 1.070s 21.078us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 2.790s 519.874us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 2.790s 519.874us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 1.120s 44.648us 5 5 100.00
i2c_csr_rw 1.130s 26.619us 20 20 100.00
i2c_csr_aliasing 1.850s 74.400us 5 5 100.00
i2c_same_csr_outstanding 2.640s 3027.280us 20 20 100.00
V2 tl_d_partial_access i2c_csr_hw_reset 1.120s 44.648us 5 5 100.00
i2c_csr_rw 1.130s 26.619us 20 20 100.00
i2c_csr_aliasing 1.850s 74.400us 5 5 100.00
i2c_same_csr_outstanding 2.640s 3027.280us 20 20 100.00
V2 TOTAL 1610 1792 89.84
V2S tl_intg_err i2c_tl_intg_err 2.640s 147.039us 20 20 100.00
i2c_sec_cm 1.350s 70.818us 5 5 100.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 2.640s 147.039us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 37.280s 1541.529us 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 3.150s 461.370us 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 12.020s 901.838us 0 10 0.00
V3 TOTAL 0 70 0.00
TOTAL 1790 2042 87.66

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
86.08 97.19 88.91 89.66 47.62 93.68 96.41 89.11

Failure Buckets