KEYMGR Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: `53b5e04`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	13.080s	799.409us	50	50	100.00
V1	random	keymgr_random	31.830s	2206.719us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.280s	128.217us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.520s	183.881us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.460s	1753.079us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.250s	377.072us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.980s	84.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.520s	183.881us	20	20	100.00
		keymgr_csr_aliasing	9.250s	377.072us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	78.040s	38657.637us	49	50	98.00
V2	sideload	keymgr_sideload	22.900s	4901.737us	50	50	100.00
		keymgr_sideload_kmac	48.360s	7544.265us	50	50	100.00
		keymgr_sideload_aes	28.970s	3695.927us	50	50	100.00
		keymgr_sideload_otbn	37.140s	9944.946us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.630s	4022.517us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.540s	113.821us	46	50	92.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.630s	948.538us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	39.880s	2445.924us	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	29.570s	1819.584us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	7.790s	624.292us	50	50	100.00
V2	stress_all	keymgr_stress_all	386.130s	55894.497us	48	50	96.00
V2	intr_test	keymgr_intr_test	1.100s	12.379us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.320s	20.392us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.570s	133.711us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.570s	133.711us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.280s	128.217us	5	5	100.00
		keymgr_csr_rw	1.520s	183.881us	20	20	100.00
		keymgr_csr_aliasing	9.250s	377.072us	5	5	100.00
		keymgr_same_csr_outstanding	2.890s	111.506us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.280s	128.217us	5	5	100.00
		keymgr_csr_rw	1.520s	183.881us	20	20	100.00
		keymgr_csr_aliasing	9.250s	377.072us	5	5	100.00
		keymgr_same_csr_outstanding	2.890s	111.506us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	sec_cm_additional_check	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	tl_intg_err	keymgr_tl_intg_err	7.990s	1569.067us	20	20	100.00
		keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.210s	334.541us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.210s	334.541us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.210s	334.541us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.210s	334.541us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.270s	5062.403us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.990s	1569.067us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.210s	334.541us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	78.040s	38657.637us	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_csr_rw	1.520s	183.881us	20	20	100.00
		keymgr_random	31.830s	2206.719us	50	50	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_csr_rw	1.520s	183.881us	20	20	100.00
		keymgr_random	31.830s	2206.719us	50	50	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_csr_rw	1.520s	183.881us	20	20	100.00
		keymgr_random	31.830s	2206.719us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.540s	113.821us	46	50	92.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	29.570s	1819.584us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	29.570s	1819.584us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	31.830s	2206.719us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	17.480s	1789.955us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	17.580s	1078.696us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.540s	113.821us	46	50	92.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	17.580s	1078.696us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	17.580s	1078.696us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	17.580s	1078.696us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.180s	1162.943us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	17.580s	1078.696us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.100s	2882.538us	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1079	1110	97.21

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.13	98.22	98.65	100.00	99.01	97.71	91.13

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.100120325748139866600482318146241358373804268906271552700920159831365797225665
    Line 267, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 239254712 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 239254712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.110853223017092558968709190742938055328444121829233089507914230791195889315100
    Line 194, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109616083 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 109616083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 2 failures:

Test keymgr_stress_all has 1 failures.

15.keymgr_stress_all.12540698932136709028345247003330339954902695957864927871280410179422567768650
Line 695, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 195575231 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 195575231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

40.keymgr_lc_disable.115258132987855908129874235974720970595407159621846575653826282078363730242329
Line 282, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 198796620 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (451683514 [0x1aec24ba] vs 451683514 [0x1aec24ba]) reg name: keymgr_reg_block.sw_share0_output_6
  UVM_INFO @ 198796620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_sw_invalid_input has 1 failures.
  - 19.keymgr_sw_invalid_input.25852916397357780401349954688028988935450706594627199625390164889534761300735
    Line 208, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @  21189030 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  21189030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_cfg_regwen has 1 failures.
  - 44.keymgr_cfg_regwen.74787140339569743685637770679782156448620200119235141947242905378673343676869
    Line 373, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @  28275684 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  28275684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 8.keymgr_lc_disable.103182946372220277983941323563089166952988577298432613993874183165900716812244
    Line 157, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  27417684 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @  27417684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

10.keymgr_stress_all.114259382218849082877934244453893098443932453588733506293382622127402102168823
Line 922, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1115015315 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (6600015597886458818962536472920951108556970457316757066271589626872994926662054048149040385178715512223245414901334508972852127304018138921907273861794299 [0x7e04344909251cce04f8b04cffefc1a5c491561d3f1ee409c4acbe4919d6ff68148635828002c193f1bf62f29ba721624793bfbbf5d2c41f35de1f45218989fb] vs 6600015597886458818962536472920951108556970457316757066271589626872994926662054048149040385178715512223245414901334508972852127304018138921907273861794299 [0x7e04344909251cce04f8b04cffefc1a5c491561d3f1ee409c4acbe4919d6ff68148635828002c193f1bf62f29ba721624793bfbbf5d2c41f35de1f45218989fb]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @ 1115015315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 21.keymgr_lc_disable.109460505150906288025909548815666931847644926590797616006549101442440117083242
    Line 88, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @   6533197 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @   6533197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

35.keymgr_lc_disable.10150765686011077867590671593984024927288846213625153551975715436819632078520
Line 307, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  33414060 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3106871676131705831645338021670586284177652973289805192034787913055495984750603964080578347256285029730259253159962466584037903874289095214063757968132026 [0x3b521289dead909e2da588173fb9f017bba6f20df45a3c0538436e804b22ad53179324b8ad0c0be2729a2b05d0066a62c98c24c0a5e78f767c19dacf3fb5c7ba] vs 3106871676131705831645338021670586284177652973289805192034787913055495984750603964080578347256285029730259253159962466584037903874289095214063757968132026 [0x3b521289dead909e2da588173fb9f017bba6f20df45a3c0538436e804b22ad53179324b8ad0c0be2729a2b05d0066a62c98c24c0a5e78f767c19dacf3fb5c7ba]) AES key at state StOwnerKey for Sealing Aes
  UVM_INFO @  33414060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---