KMAC/UNMASKED Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	104.630s	33064.608us	100	100	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.510s	36.678us	10	10	100.00
V1	csr_rw	kmac_csr_rw	1.580s	126.247us	40	40	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.160s	5782.567us	10	10	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.840s	1653.937us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.140s	101.695us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	126.247us	40	40	100.00
		kmac_csr_aliasing	10.840s	1653.937us	10	10	100.00
V1	mem_walk	kmac_mem_walk	1.110s	16.323us	10	10	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.690s	111.095us	10	10	100.00
V1		TOTAL			230	230	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4039.730s	516684.216us	100	100	100.00
V2	burst_write	kmac_burst_write	1347.920s	34930.213us	100	100	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	2003.900s	119025.525us	10	10	100.00
		kmac_test_vectors_sha3_256	1959.950s	310571.867us	10	10	100.00
		kmac_test_vectors_sha3_384	1609.160s	249144.205us	10	10	100.00
		kmac_test_vectors_sha3_512	973.680s	95710.592us	10	10	100.00
		kmac_test_vectors_shake_128	2414.950s	107746.477us	10	10	100.00
		kmac_test_vectors_shake_256	2057.930s	88476.900us	10	10	100.00
		kmac_test_vectors_kmac	4.240s	535.716us	10	10	100.00
		kmac_test_vectors_kmac_xof	3.450s	78.450us	10	10	100.00
V2	sideload	kmac_sideload	457.040s	22582.629us	100	100	100.00
V2	app	kmac_app	414.540s	50772.413us	100	100	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	350.170s	19146.530us	20	20	100.00
V2	entropy_refresh	kmac_entropy_refresh	352.300s	27095.371us	100	100	100.00
V2	error	kmac_error	532.970s	19646.555us	97	100	97.00
V2	key_error	kmac_key_error	22.220s	29560.297us	100	100	100.00
V2	sideload_invalid	kmac_sideload_invalid	137.700s	10021.852us	90	100	90.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.720s	4087.062us	40	40	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.480s	1403.084us	40	40	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	84.620s	12626.470us	20	20	100.00
V2	lc_escalation	kmac_lc_escalation	68.160s	3780.493us	100	100	100.00
V2	stress_all	kmac_stress_all	3250.580s	426614.069us	100	100	100.00
V2	intr_test	kmac_intr_test	1.230s	156.200us	100	100	100.00
V2	alert_test	kmac_alert_test	1.320s	152.638us	100	100	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.660s	186.900us	40	40	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.660s	186.900us	40	40	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.510s	36.678us	10	10	100.00
		kmac_csr_rw	1.580s	126.247us	40	40	100.00
		kmac_csr_aliasing	10.840s	1653.937us	10	10	100.00
		kmac_same_csr_outstanding	3.160s	215.151us	40	40	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.510s	36.678us	10	10	100.00
		kmac_csr_rw	1.580s	126.247us	40	40	100.00
		kmac_csr_aliasing	10.840s	1653.937us	10	10	100.00
		kmac_same_csr_outstanding	3.160s	215.151us	40	40	100.00
V2		TOTAL			1467	1480	99.12
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.840s	307.018us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.840s	307.018us	40	40	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.840s	307.018us	40	40	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.840s	307.018us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.170s	965.182us	39	40	97.50
V2S	tl_intg_err	kmac_tl_intg_err	6.010s	302.138us	40	40	100.00
		kmac_sec_cm	68.760s	6031.955us	10	10	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.010s	302.138us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	68.160s	3780.493us	100	100	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	104.630s	33064.608us	100	100	100.00
V2S	sec_cm_key_sideload	kmac_sideload	457.040s	22582.629us	100	100	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.840s	307.018us	40	40	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	68.760s	6031.955us	10	10	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	68.760s	6031.955us	10	10	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	68.760s	6031.955us	10	10	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	104.630s	33064.608us	100	100	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	68.160s	3780.493us	100	100	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	68.760s	6031.955us	10	10	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	269.550s	71030.144us	20	20	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	104.630s	33064.608us	100	100	100.00
V2S		TOTAL			149	150	99.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	304.360s	18112.286us	16	20	80.00
V3		TOTAL			16	20	80.00
		TOTAL			1862	1880	99.04

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.81	97.69	94.41	100.00	74.38	96.04	97.74	96.40

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test kmac_error has 3 failures.

    • 1.kmac_error.99671457286137903986176213293369068184995977143136379491552052034981100865179
      Line 208, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.kmac_error.112562556767555465384403957319763726795480180344881330234940805815713564372255
      Line 237, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 3 failures:

  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 9.kmac_stress_all_with_rand_reset.875345028250664940374539197903205338977832710202160426613451910465970467941
      Line 272, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8144416059 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 8144416059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.kmac_stress_all_with_rand_reset.32551849031295981666268298821332753684264430743706527793700799113000958717500
      Line 382, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11531326763 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 11531326763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 11.kmac_sideload_invalid.114665680283451357614971187767171720596573757897709694796390023175215268218651
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10040804629 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdbbf9000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10040804629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 30.kmac_sideload_invalid.15280197026990291013045158706079091762935646676077602042808922756668905749049
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10138274578 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x94ca0000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10138274578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 7.kmac_stress_all_with_rand_reset.100816601121289920214554547291086902141804791232174536104530596596002079651490
      Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1850402982 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1850402982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 8.kmac_sideload_invalid.103929249429458309412709440356109905423118397460774019319640608267107159496509
      Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10613993882 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6a97c000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10613993882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 12.kmac_sideload_invalid.22088748225209749654393191702657869434452094417387376999500725593906162932418
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10073813836 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaf35e000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
        UVM_INFO @ 10073813836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 15.kmac_sideload_invalid.59602462709064721836861400877630501674724000132394433566340875463315376310264
      Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10449473009 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdb4bc000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
        UVM_INFO @ 10449473009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 27.kmac_sideload_invalid.61427201013537613496046516844995286091829479098586073190764232895323315736791
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10019862258 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf596f000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10019862258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 28.kmac_sideload_invalid.15212859890690873933104966296525791068904079471207881381171901079077310650333
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10021852495 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3fe03000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10021852495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 32.kmac_sideload_invalid.24582012101627785048303623706222115172496794714409932762430123728381269188674
      Line 95, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10188267861 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5eeb8000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
        UVM_INFO @ 10188267861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 35.kmac_sideload_invalid.12757582541466552963564965133350282810602232769108948358153454982334052295793
      Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10088112823 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe2b77000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
        UVM_INFO @ 10088112823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 43.kmac_sideload_invalid.50393728999276653281728716504808908648101020661985305974396613022092575337740
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10025775114 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x64e0e000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10025775114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 11.kmac_shadow_reg_errors_with_csr_rw.115489389277347026660953676747054224483367169317431208655812590679741323748603
      Line 286, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 198505831 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3349230217 [0xc7a13289] vs 2148706333 [0x8012a81d]) Regname: kmac_reg_block.prefix_5.prefix_0 reset value: 0x0
        UVM_INFO @ 198505831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---