MBX Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: 53b5e04

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 99.000s 5174.827us 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 2.000s 30.386us 5 5 100.00
V1 csr_rw mbx_csr_rw 2.000s 13.871us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 6.000s 561.074us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 2.000s 18.403us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 3.000s 132.758us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 2.000s 13.871us 20 20 100.00
mbx_csr_aliasing 2.000s 18.403us 5 5 100.00
V1 TOTAL 57 57 100.00
V2 mbx_stress mbx_stress 14.000s 3700.478us 0 2 0.00
V2 mbx_max_activity mbx_stress_zero_delays 138.000s 34965.820us 1 2 50.00
V2 mbx_imbx_oob mbx_imbx_oob 8.000s 682.045us 0 2 0.00
V2 mbx_doe_intr_msg mbx_doe_intr_msg 25.000s 541.928us 5 5 100.00
V2 alert_test mbx_alert_test 2.000s 24.837us 50 50 100.00
V2 intr_test mbx_intr_test 2.000s 44.549us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 7.000s 2534.679us 20 20 100.00
V2 tl_d_illegal_access mbx_tl_errors 7.000s 2534.679us 20 20 100.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 2.000s 30.386us 5 5 100.00
mbx_csr_rw 2.000s 13.871us 20 20 100.00
mbx_csr_aliasing 2.000s 18.403us 5 5 100.00
mbx_same_csr_outstanding 3.000s 39.755us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 2.000s 30.386us 5 5 100.00
mbx_csr_rw 2.000s 13.871us 20 20 100.00
mbx_csr_aliasing 2.000s 18.403us 5 5 100.00
mbx_same_csr_outstanding 3.000s 39.755us 20 20 100.00
V2 TOTAL 146 151 96.69
V2S tl_intg_err mbx_sec_cm 2.000s 52.455us 5 5 100.00
mbx_tl_intg_err 3.000s 238.496us 20 20 100.00
V2S TOTAL 25 25 100.00
TOTAL 228 233 97.85

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.93 95.53 88.83 95.98 90.99 86.12 -- 97.01 85.35

Failure Buckets