53b5e04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 11.000s | 898.716us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 32.795us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 10.000s | 16.352us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 6.000s | 124.842us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 4.000s | 17.038us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 754.439us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 10.000s | 16.352us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 4.000s | 17.038us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 45.000s | 6154.707us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 15.000s | 249.816us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 36.000s | 159.903us | 9 | 10 | 90.00 |
| V2 | multi_error | otbn_multi_err | 76.000s | 263.637us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 188.000s | 700.292us | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 97.000s | 214.442us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 21.000s | 209.624us | 59 | 60 | 98.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 129.748us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 54.000s | 192.245us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 5.000s | 17.193us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 7.000s | 28.296us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 9.000s | 84.393us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 9.000s | 84.393us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 32.795us | 5 | 5 | 100.00 |
| otbn_csr_rw | 10.000s | 16.352us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 4.000s | 17.038us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 34.307us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 32.795us | 5 | 5 | 100.00 |
| otbn_csr_rw | 10.000s | 16.352us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 4.000s | 17.038us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 34.307us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 243 | 246 | 98.78 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 41.531us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 46.051us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 24.000s | 69.099us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 11.000s | 122.132us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 21.000s | 95.103us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 52.892us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 18.065s | 0.000us | 4 | 5 | 80.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 15.521us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 7.000s | 104.234us | 10 | 10 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| otbn_tl_intg_err | 33.000s | 220.653us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 69.000s | 420.405us | 18 | 20 | 90.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | prim_count_check | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 11.000s | 898.716us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 16.000s | 46.051us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 41.531us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 33.000s | 220.653us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 21.000s | 209.624us | 59 | 60 | 98.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 41.531us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 46.051us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 129.748us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 18.065s | 0.000us | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 41.531us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 46.051us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 129.748us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 18.065s | 0.000us | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 21.000s | 209.624us | 59 | 60 | 98.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 41.531us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 46.051us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 129.748us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 18.065s | 0.000us | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 16.000s | 80.467us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 27.348us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 121.000s | 942.455us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 121.000s | 942.455us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 35.948us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 12.000s | 69.773us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 11.000s | 95.001us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 11.000s | 95.001us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 25.000s | 65.783us | 4 | 7 | 57.14 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 188.000s | 700.292us | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 23.000s | 81.847us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 404.000s | 1627.875us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 206.000s | 3451.680us | 2 | 5 | 40.00 |
| V2S | TOTAL | 154 | 163 | 94.48 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 520.000s | 2625.385us | 2 | 10 | 20.00 |
| V3 | TOTAL | 2 | 10 | 20.00 | |||
| TOTAL | 565 | 585 | 96.58 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 99.01 | 99.59 | 95.20 | 99.67 | 93.13 | 93.25 | 97.44 | 96.84 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
0.otbn_stress_all_with_rand_reset.70661012962014234040251124565922227870962099162330561383749863912262746183442
Line 190, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 366624796 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 366624796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_stress_all_with_rand_reset.73454703018136545661749668714126342751533418688574850093561740934508684435248
Line 357, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1217573306 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1217573306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
1.otbn_sec_wipe_err.76905453890090906616197194240005340668026851903768804816412033708216535039601
Line 111, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19291037 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 19291037 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19291037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_sec_wipe_err.63103452478501305162656552871478446600584499047687572893787992992116452036100
Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 75854492 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 75854492 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 75854492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
27.otbn_escalate.5554137616905660464754478440574589046221606674424231385411829200669730095387
Line 121, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17175829 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 17175829 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17175829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:
0.otbn_sec_cm.64158362387906175132376712533052721091686169061939460598941203578161916226972
Line 89, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 17288073 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 17288073 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 17288073 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 17288073 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 17288073 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
1.otbn_sec_cm.59518444422598174597308119642876927516604451526070481436113419282389687726377
Line 92, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 43009240 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 43009240 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 43009240 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 43009240 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 43009240 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 3 failures:
Test otbn_reset has 1 failures.
2.otbn_reset.83172208018535576771777718344370178964225232502143699961374487991145357068305
Line 138, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_reset/latest/run.log
UVM_FATAL @ 67281043 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 67281043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_multi has 1 failures.
8.otbn_multi.60967287550986487328896652776013883346852400394935261388078195871359701918573
Line 176, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_multi/latest/run.log
UVM_FATAL @ 825023315 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 825023315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_passthru_mem_tl_intg_err has 1 failures.
3.otbn_passthru_mem_tl_intg_err.23292460493016530391509818211299129737755861351267435787675697102824737806986
Line 93, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 39385132 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 39385132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
0.otbn_illegal_mem_acc.24570022656618627131894699515519552403963084118617761169607385478227151629889
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest/run.log
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 24570022656618627131894699515519552403963084118617761169607385478227151629889 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3703647809 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_illegal_mem_acc_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_illegal_mem_acc.3703647809 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_illegal_mem_acc.3703647809 -covoverwrite' seed=24570022656618627131894699515519552403963084118617761169607385478227151629889 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_illegal_mem_acc_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 24570022656618627131894699515519552403963084118617761169607385478227151629889 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_illegal_mem_acc/latest
2025/11/15 08:16:33 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
4.otbn_passthru_mem_tl_intg_err.56850203038482089370394464216048026669862812833908717489496970977820093517239
Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 13703520 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 13703520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---