ROM_CTRL/32KB Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: `53b5e04`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	11.630s	1112.187us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.470s	4165.468us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.200s	955.052us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.450s	561.322us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.880s	588.653us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.420s	309.851us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.200s	955.052us	40	40	100.00
		rom_ctrl_csr_aliasing	10.880s	588.653us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.890s	2103.435us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.630s	301.339us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.230s	301.442us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	52.270s	5929.566us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	22.580s	3844.720us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	14.840s	1874.680us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.110s	287.753us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.110s	287.753us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.470s	4165.468us	10	10	100.00
		rom_ctrl_csr_rw	11.200s	955.052us	40	40	100.00
		rom_ctrl_csr_aliasing	10.880s	588.653us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.380s	297.848us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.470s	4165.468us	10	10	100.00
		rom_ctrl_csr_rw	11.200s	955.052us	40	40	100.00
		rom_ctrl_csr_aliasing	10.880s	588.653us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.380s	297.848us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	63.400s	1635.547us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	535.190s	983.831us	0	10	0.00
		rom_ctrl_tl_intg_err	126.130s	2401.112us	40	40	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	535.190s	983.831us	0	10	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	535.190s	983.831us	0	10	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	535.190s	983.831us	0	10	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	535.190s	983.831us	0	10	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	11.630s	1112.187us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	11.630s	1112.187us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	11.630s	1112.187us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	126.130s	2401.112us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
		rom_ctrl_kmac_err_chk	22.580s	3844.720us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	227.890s	6573.582us	38	40	95.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	63.400s	1635.547us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	535.190s	983.831us	0	10	0.00
V2S		TOTAL			118	130	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	633.190s	16137.201us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			520	532	97.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 4 failures:

Test rom_ctrl_sec_cm has 4 failures.

1.rom_ctrl_sec_cm.12774171088419702972214545641856746724906417447917210331881955916977305469174
Line 115, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 2756861ps failed at 2756861ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 4439894ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 4439894ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))

3.rom_ctrl_sec_cm.57444122231524874360065470797280679223773110724756660047816020764215251406492
Line 550, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 140809637ps failed at 140809637ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 140844120ps failed at 140844120ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

... and 2 more failures.

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'

has 3 failures:

Test rom_ctrl_sec_cm has 3 failures.

0.rom_ctrl_sec_cm.22876469678745670748769996203166152091947411581262973202414896255977336103066
Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3972018ps failed at 3972018ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3972018ps failed at 3972018ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

0.rom_ctrl_sec_cm.46890202946169158979263449081086749508479979574656289779273272402192067120791
Line 544, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 69616099ps failed at 69616099ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 69616099ps failed at 69616099ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

... and 1 more failures.

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 3 failures:

Test rom_ctrl_sec_cm has 3 failures.

2.rom_ctrl_sec_cm.59328471979523645165542425521164262152493890476469328342092580431788624546678
Line 227, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 10939467ps failed at 10939467ps
      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 10939467ps failed at 10939467ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'

2.rom_ctrl_sec_cm.109019437431974921770281063355775070239997853038833908233367889232910529150661
Line 301, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16877243ps failed at 16877243ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 18905935ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 18905935ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))

... and 1 more failures.

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 9.rom_ctrl_corrupt_sig_fatal_chk.63306549878193142345657832512260379623087793135006360250350619194529720886370
    Line 96, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1097855780 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1097855780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.rom_ctrl_corrupt_sig_fatal_chk.34692236757454674619119759442634354656277296712497741385896035378791637273255
    Line 97, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 5302908228 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 5302908228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```