RV_TIMER Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: `53b5e04`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.480s	1146.158us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.810s	66.921us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.880s	52.736us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.170s	737.137us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.080s	276.269us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.350s	117.452us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.880s	52.736us	20	20	100.00
		rv_timer_csr_aliasing	1.080s	276.269us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	5.580s	7416.247us	2	20	10.00
V2	disabled	rv_timer_disabled	3.820s	2387.272us	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	306.360s	679198.013us	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	306.360s	679198.013us	10	10	100.00
V2	stress	rv_timer_stress_all	6.330s	4050.385us	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.900s	39.267us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.880s	22.101us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.530s	61.728us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.530s	61.728us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.810s	66.921us	5	5	100.00
		rv_timer_csr_rw	0.880s	52.736us	20	20	100.00
		rv_timer_csr_aliasing	1.080s	276.269us	5	5	100.00
		rv_timer_same_csr_outstanding	1.000s	146.400us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.810s	66.921us	5	5	100.00
		rv_timer_csr_rw	0.880s	52.736us	20	20	100.00
		rv_timer_csr_aliasing	1.080s	276.269us	5	5	100.00
		rv_timer_same_csr_outstanding	1.000s	146.400us	20	20	100.00
V2		TOTAL			192	210	91.43
V2S	tl_intg_err	rv_timer_sec_cm	1.340s	107.721us	5	5	100.00
		rv_timer_tl_intg_err	1.350s	974.309us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.350s	974.309us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.960s	1614.042us	1	10	10.00
V3	max_value	rv_timer_max	1.450s	753.108us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	42.780s	17926.442us	15	20	75.00
V3		TOTAL			16	40	40.00
		TOTAL			308	350	88.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	100.00	100.00	100.00	--	100.00	96.82	98.53

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
- Test rv_timer_min has 9 failures.
  - 0.rv_timer_min.48006891484336823909208098286808215569415489241324336396777047226871504018509
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 204884114 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x96e35f04) == 0x1
  UVM_INFO @ 204884114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_min.1543763001659807655733085317419635472987016194338294183872262986866348600800
    Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 130190898 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4dfa1d04) == 0x1
  UVM_INFO @ 130190898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
- Test rv_timer_random_reset has 18 failures.
  - 0.rv_timer_random_reset.102679432571549792737359617686322312798123774132747852180830678691477149932573
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 606317459 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x33498f04) == 0x1
  UVM_INFO @ 606317459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.79026107070558489698271088307386397946944010753310987141252485708345529506928
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 877111708 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x63606704) == 0x1
  UVM_INFO @ 877111708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
- Test rv_timer_max has 10 failures.
  - 0.rv_timer_max.89023295390713262747015720587674218614630371352182160352608610177897119077990
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 181630716 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 181630716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.91402211421370679090253024604548715422249554850740261971296821460053485261282
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 169298283 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 169298283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 3 failures:
- Test rv_timer_stress_all_with_rand_reset has 3 failures.
  - 3.rv_timer_stress_all_with_rand_reset.56543227237165458482780193580809830923512507084400418386388337538605546184510
    Line 95, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1140659254 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 1140659254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.rv_timer_stress_all_with_rand_reset.44627149281198087832689354245044835654620279946210175005936727122572631969102
    Line 119, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1057514866 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 1057514866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

0.rv_timer_stress_all_with_rand_reset.100900320990165183079248437685909015275187047324636582449238318777120688515552
Line 148, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4263273357 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4263273357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rv_timer_stress_all_with_rand_reset.68355858794902388551381142190584894374334634541446325087499941465277938216144
Line 100, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1339612671 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1339612671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---