SPI_DEVICE/1R1W Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: `53b5e04`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	497.120s	1500000.000us	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.300s	219.747us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.490s	39.332us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.040s	14239.518us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.800s	928.153us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.390s	203.020us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.490s	39.332us	20	20	100.00
		spi_device_csr_aliasing	16.800s	928.153us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.040s	38.756us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.630s	158.329us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	1.200s	17.931us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	4.824us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.850s	4.703us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.100s	154.960us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.100s	154.960us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.060s	169237.081us	50	50	100.00
		spi_device_tpm_sts_read	1.570s	472.075us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.180s	8915.447us	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.200s	56346.164us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	26.430s	42362.100us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	26.430s	42362.100us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.280s	31427.207us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.280s	31427.207us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.280s	31427.207us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.280s	31427.207us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.280s	31427.207us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	33.860s	36381.689us	50	50	100.00
V2	mailbox_command	spi_device_mailbox	108.850s	41405.681us	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	108.850s	41405.681us	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	108.850s	41405.681us	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	65.780s	4393.819us	50	50	100.00
		spi_device_read_buffer_direct	21.630s	13149.495us	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	108.850s	41405.681us	50	50	100.00
		spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	quad_spi	spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	dual_spi	spi_device_flash_all	430.220s	340448.924us	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.720s	25562.365us	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	28.720s	25562.365us	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	497.120s	1500000.000us	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	502.340s	65856.752us	50	50	100.00
V2	stress_all	spi_device_stress_all	656.360s	488787.564us	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	14.558us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.090s	28.664us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.010s	755.071us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.010s	755.071us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.300s	219.747us	5	5	100.00
		spi_device_csr_rw	2.490s	39.332us	20	20	100.00
		spi_device_csr_aliasing	16.800s	928.153us	5	5	100.00
		spi_device_same_csr_outstanding	3.740s	56.707us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.300s	219.747us	5	5	100.00
		spi_device_csr_rw	2.490s	39.332us	20	20	100.00
		spi_device_csr_aliasing	16.800s	928.153us	5	5	100.00
		spi_device_same_csr_outstanding	3.740s	56.707us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_tl_intg_err	18.500s	2595.409us	20	20	100.00
		spi_device_sec_cm	1.640s	307.912us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.500s	2595.409us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	342.390s	597828.802us	50	50	100.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.37	99.11	96.56	83.54	89.36	98.40	94.43	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.61195600232508324112499832929984670732945402882760015251960653558174880212318
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1576017 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[68])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1576017 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1576017 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[964])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.102471618491049704438694984328948583142626129890447487994588033510760277101200
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  11314033 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[102])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  11314033 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  11314033 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[998])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.29156323340612344079127741048644356957396082750693440305131275162911275165360
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   2479039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcff112 [110011111111000100010010] vs 0x0 [0])
  UVM_ERROR @   2567039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5d0d5a [10111010000110101011010] vs 0x0 [0])
  UVM_ERROR @   2615039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb73f33 [101101110011111100110011] vs 0x0 [0])
  UVM_ERROR @   2626039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd2c184 [110100101100000110000100] vs 0x0 [0])
  UVM_ERROR @   2726039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x201e53 [1000000001111001010011] vs 0x0 [0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm has 1 failures.
  - 35.spi_device_flash_and_tpm.74980871170496883469258821465255654240875095199992534542918718223369951725096
    Line 130, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

43.spi_device_cfg_cmd.96384608973640981513553843386007629214725476483647530498404640643326633429628
Line 77, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  32293875 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x14114a) != exp '{'{other_status:'h158247, wel:'h1, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h38f5fe, wel:'h0, busy:'h0}}
  UVM_ERROR @  32773057 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x14114a) != exp '{'{other_status:'h158247, wel:'h1, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h38f5fe, wel:'h0, busy:'h0}}
  UVM_ERROR @  33106401 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x14114a) != exp '{'{other_status:'h158247, wel:'h1, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h38f5fe, wel:'h0, busy:'h0}, '{other_status:'h173b76, wel:'h0, busy:'h0}}
  UVM_ERROR @  33252239 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x14114a) != exp '{'{other_status:'h158247, wel:'h1, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h50452, wel:'h0, busy:'h0}, '{other_status:'h38f5fe, wel:'h0, busy:'h0}, '{other_status:'h173b76, wel:'h0, busy:'h0}}
  UVM_INFO @  33616834 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0xe9