SPI_HOST Simulation Results

Friday November 14 2025 18:20:34 UTC

GitHub Revision: `53b5e04`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	104.000s	8921.826us	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	20.465us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	54.067us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	864.431us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	20.650us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	43.116us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	54.067us	20	20	100.00
		spi_host_csr_aliasing	2.000s	20.650us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	39.660us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	66.619us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	27.000s	21.017us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	42.000s	2546.012us	50	50	100.00
		spi_host_error_cmd	27.000s	42.817us	50	50	100.00
		spi_host_event	347.000s	121468.014us	50	50	100.00
V2	clock_rate	spi_host_speed	30.000s	325.566us	50	50	100.00
V2	speed	spi_host_speed	30.000s	325.566us	50	50	100.00
V2	chip_select_timing	spi_host_speed	30.000s	325.566us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	137.000s	4159.708us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	27.000s	135.413us	50	50	100.00
V2	cpol_cpha	spi_host_speed	30.000s	325.566us	50	50	100.00
V2	full_cycle	spi_host_speed	30.000s	325.566us	50	50	100.00
V2	duplex	spi_host_smoke	104.000s	8921.826us	50	50	100.00
V2	tx_rx_only	spi_host_smoke	104.000s	8921.826us	50	50	100.00
V2	stress_all	spi_host_stress_all	2046.000s	1000000.000us	47	50	94.00
V2	spien	spi_host_spien	196.000s	17562.269us	50	50	100.00
V2	stall	spi_host_status_stall	816.000s	263835.646us	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	50.000s	8392.097us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	42.000s	2546.012us	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	140.660us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	15.212us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	114.362us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	114.362us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	20.465us	5	5	100.00
		spi_host_csr_rw	2.000s	54.067us	20	20	100.00
		spi_host_csr_aliasing	2.000s	20.650us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	48.459us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	20.465us	5	5	100.00
		spi_host_csr_rw	2.000s	54.067us	20	20	100.00
		spi_host_csr_aliasing	2.000s	20.650us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	48.459us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_sec_cm	2.000s	299.529us	5	5	100.00
		spi_host_tl_intg_err	3.000s	260.873us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	260.873us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	820.000s	111865.486us	10	10	100.00
		TOTAL			836	840	99.52

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.15	96.82	93.35	98.69	94.15	88.02	100.00	95.21	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_stress_all has 2 failures.
  - 13.spi_host_stress_all.90722697126608938275393276232546575267572798881758421791528848852261139511108
    Line 266, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.spi_host_stress_all.20476520859332535568052217811741620901708813865564836024353437584105357413305
    Line 139, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/49.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

12.spi_host_status_stall.87766858803099957728141131741734017183673176163404610049318061523597915803042
Line 819, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 2705374683 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 2705374683 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=2705375000 ps
  UVM_INFO @ 2705374683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 16.spi_host_stress_all.1792359599027328291232368750378503367470239737497633206471803209928648511014
    Line 318, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/16.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10307477692 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xca68994, Comparison=CompareOpEq, exp_data=0x0, call_count=72
  UVM_INFO @ 10307477692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```