53b5e04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 18.920s | 5310.297us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.780s | 35.348us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.770s | 15.051us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 1.980s | 256.415us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.820s | 95.461us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 0.960s | 76.398us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.770s | 15.051us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 0.820s | 95.461us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 240.140s | 95105.751us | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 18.920s | 5310.297us | 50 | 50 | 100.00 |
| uart_tx_rx | 240.140s | 95105.751us | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 365.560s | 307180.227us | 49 | 50 | 98.00 |
| uart_rx_parity_err | 289.030s | 136101.557us | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 240.140s | 95105.751us | 50 | 50 | 100.00 |
| uart_intr | 365.560s | 307180.227us | 49 | 50 | 98.00 | ||
| V2 | fifo_full | uart_fifo_full | 685.150s | 318887.139us | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 343.570s | 176384.317us | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 585.800s | 208689.762us | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 365.560s | 307180.227us | 49 | 50 | 98.00 |
| V2 | rx_break_err | uart_intr | 365.560s | 307180.227us | 49 | 50 | 98.00 |
| V2 | rx_timeout | uart_intr | 365.560s | 307180.227us | 49 | 50 | 98.00 |
| V2 | perf | uart_perf | 1198.100s | 27960.320us | 50 | 50 | 100.00 |
| V2 | sys_loopback | uart_loopback | 23.740s | 9740.789us | 50 | 50 | 100.00 |
| V2 | line_loopback | uart_loopback | 23.740s | 9740.789us | 50 | 50 | 100.00 |
| V2 | rx_noise_filter | uart_noise_filter | 71.940s | 35661.120us | 5 | 50 | 10.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 135.890s | 72384.799us | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 41.430s | 6770.862us | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 58.260s | 7981.917us | 50 | 50 | 100.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 1265.200s | 167926.223us | 50 | 50 | 100.00 |
| V2 | stress_all | uart_stress_all | 781.660s | 130530.894us | 31 | 50 | 62.00 |
| V2 | alert_test | uart_alert_test | 0.950s | 13.195us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.750s | 15.263us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 1.960s | 100.124us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 1.960s | 100.124us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.780s | 35.348us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.770s | 15.051us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.820s | 95.461us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.820s | 52.189us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.780s | 35.348us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.770s | 15.051us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.820s | 95.461us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.820s | 52.189us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1025 | 1090 | 94.04 | |||
| V2S | tl_intg_err | uart_tl_intg_err | 1.150s | 1058.828us | 20 | 20 | 100.00 |
| uart_sec_cm | 1.200s | 181.839us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.150s | 1058.828us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 96.340s | 16109.662us | 85 | 100 | 85.00 |
| V3 | TOTAL | 85 | 100 | 85.00 | |||
| TOTAL | 1240 | 1320 | 93.94 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.34 | 99.48 | 98.25 | 91.55 | -- | 98.14 | 97.12 | 99.50 |
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 41 failures:
3.uart_noise_filter.74155896529244419314871938784406050217887830573408616771849068032940935831791
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log
UVM_ERROR @ 1530077389 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1530077389 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2372613087 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 2
UVM_ERROR @ 2372631269 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2372649451 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 161 [0xa1]) reg name: uart_reg_block.rdata
4.uart_noise_filter.66396631698062714278561401993476099667537545675254570674026830633236457800848
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log
UVM_ERROR @ 10348144 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10510306 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 13077871 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 20645431 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 21510295 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 17 more failures.
6.uart_stress_all.74586836652828092873998123430714849957731206116988514067903783007704233684861
Line 86, in log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_stress_all/latest/run.log
UVM_ERROR @ 72755270020 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 72976313455 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 72976313455 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 74019030130 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 74019030130 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
7.uart_stress_all.10794378753984578465636915275554204517392401692377536598129199812772704428606
Line 87, in log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_stress_all/latest/run.log
UVM_ERROR @ 129124789177 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 129124789177 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 129169303631 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 129310552025 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 129310573077 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (71 [0x47] vs 175 [0xaf]) reg name: uart_reg_block.rdata
... and 11 more failures.
13.uart_stress_all_with_rand_reset.18894613396672687912686875465907890778829578043623381713283894415524845800475
Line 102, in log /nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2007389647 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2015657857 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2016145657 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2016511507 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2016901747 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
22.uart_stress_all_with_rand_reset.93046373154826244788843177566280660301730013158821635094158743614211321725972
Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 444250872 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 444250872 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 497751300 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 553585080 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 553668414 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (27 [0x1b] vs 191 [0xbf]) reg name: uart_reg_block.rdata
... and 7 more failures.
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 14 failures:
10.uart_noise_filter.77419999944924309355383940029821170832539232303666506167577598698879632326289
Line 83, in log /nightly/current_run/scratch/master/uart-sim-vcs/10.uart_noise_filter/latest/run.log
UVM_ERROR @ 40759220614 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 40759266069 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 40759447889 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (130 [0x82] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 41326317194 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 41326317194 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
19.uart_noise_filter.85942933550259302362702706766292331830404960353322810760230063581898318092445
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/19.uart_noise_filter/latest/run.log
UVM_ERROR @ 90773116673 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 90773158340 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 90773200007 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (175 [0xaf] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 90775700027 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR @ 90775741694 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
... and 8 more failures.
23.uart_stress_all.1466964441556404389348393047386516496518731587783239366289115239377464508766
Line 105, in log /nightly/current_run/scratch/master/uart-sim-vcs/23.uart_stress_all/latest/run.log
UVM_ERROR @ 133399172853 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 133399183270 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 133399193687 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (248 [0xf8] vs 189 [0xbd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 133633669940 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 133633669940 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
45.uart_stress_all.108382207536696891081755771969349858524190253423182784184381548626152596020868
Line 119, in log /nightly/current_run/scratch/master/uart-sim-vcs/45.uart_stress_all/latest/run.log
UVM_ERROR @ 361251190338 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 361251227375 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 361251264412 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (77 [0x4d] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 361295116220 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 361295116220 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
... and 1 more failures.
89.uart_stress_all_with_rand_reset.99766452298373620498394809847583704534778188424660340053654453242980104597735
Line 140, in log /nightly/current_run/scratch/master/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8003593195 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 8003633195 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 8003673195 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_INFO @ 8140833195 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/487
UVM_ERROR @ 8255193195 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 13 failures:
Test uart_noise_filter has 11 failures.
0.uart_noise_filter.887389388922593150785397867579738570474028284490348706704742200795555520543
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log
UVM_ERROR @ 252806863 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 252806863 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 252806863 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 296433082 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 316493668 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
2.uart_noise_filter.75769205155964130846915247271300759367723775519296099695225903208551366130176
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log
UVM_ERROR @ 21214344227 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 21214344227 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 21214344227 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 21765906135 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 21765906135 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
... and 9 more failures.
Test uart_stress_all has 1 failures.
9.uart_stress_all.10164928820045009724815505629520800854189494094730075745305690746119320142415
Line 90, in log /nightly/current_run/scratch/master/uart-sim-vcs/9.uart_stress_all/latest/run.log
UVM_ERROR @ 22657079558 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 22657079558 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 22657079558 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 22675204703 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 9, clk_pulses: 8
UVM_ERROR @ 22675246370 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
Test uart_stress_all_with_rand_reset has 1 failures.
29.uart_stress_all_with_rand_reset.95994205779557154420428108800767091575790533192400290961375022831059449372417
Line 141, in log /nightly/current_run/scratch/master/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2497576566 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 2497576566 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2497576566 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2515984582 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/86
UVM_ERROR @ 2584412606 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (133 [0x85] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 4 failures:
1.uart_noise_filter.77833684585169930114482874103561872454903174570533843435626890193566747830002
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log
UVM_ERROR @ 329089252 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 329089252 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 600369252 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 600369252 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 828049252 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/1
11.uart_noise_filter.89014100563724514769363582374372108147523950041915423435527903575265365813791
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log
UVM_ERROR @ 65126262 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 65126262 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 165972394 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 165982598 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 165992802 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:1142) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
14.uart_stress_all_with_rand_reset.37631747599301100064453976296163243389388746022834127749623896090995860848097
Line 79, in log /nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 438298998 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 438298998 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 438381470 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 1/10
43.uart_stress_all_with_rand_reset.67752888631755057663490691817741519094170558940827282779242318799765911693504
Line 88, in log /nightly/current_run/scratch/master/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1592015018 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1592015018 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1592087181 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 2/10
... and 1 more failures.
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:
2.uart_stress_all.72720864099548425270910793845593799058251283601985017091993310116786857531491
Line 126, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_stress_all/latest/run.log
UVM_ERROR @ 268976149091 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 308165277984 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/8
UVM_INFO @ 327891149819 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/8
UVM_INFO @ 336087097739 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/8
UVM_INFO @ 361699823904 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/8
30.uart_stress_all.26579617369904651502418991000995369460182545038072303157908994812711950546832
Line 94, in log /nightly/current_run/scratch/master/uart-sim-vcs/30.uart_stress_all/latest/run.log
UVM_ERROR @ 24547920950 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 28367540950 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/10
UVM_INFO @ 28427890950 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/10
UVM_INFO @ 29365590950 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/10
UVM_INFO @ 33171330950 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/10
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxDone has 1 failures:
15.uart_intr.3593235487220552145962087442873149616986141393515436056440363337807979809737
Line 106, in log /nightly/current_run/scratch/master/uart-sim-vcs/15.uart_intr/latest/run.log
UVM_ERROR @ 13417210893 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxDone
UVM_INFO @ 13422210903 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing RxFrameErr
UVM_INFO @ 13514877755 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/3
UVM_INFO @ 13519377764 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 1 failures:
26.uart_noise_filter.93847887690825257165960281154953229246872268506943883174427802722900782947325
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/26.uart_noise_filter/latest/run.log
UVM_ERROR @ 9367346076 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 9369468006 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 9379736196 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 9379760586 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 9379858146 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR (cip_base_vseq.sv:1229) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
44.uart_stress_all_with_rand_reset.45260119897006160247596178019044074439654930636625214281929607087629072889238
Line 114, in log /nightly/current_run/scratch/master/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1877033260 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1877045667 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1877045667 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 1877053668 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2