53b5e04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 178.358s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 178.358s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 146.032s | 0.000us | 0 | 20 | 0.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 107.588s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 427.350s | 273.292us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 427.350s | 273.292us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 427.350s | 273.292us | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 39.620s | 10.360us | 0 | 3 | 0.00 |
| chip_sw_example_manufacturer | 168.729s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_example_concurrency | 224.510s | 150.358us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 14.460s | 0.000us | 0 | 3 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 15.840s | 0.000us | 0 | 3 | 0.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 15.700s | 0.000us | 0 | 3 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 15.700s | 0.000us | 0 | 3 | 0.00 |
| V1 | xbar_smoke | xbar_smoke | 39.240s | 68.335us | 100 | 100 | 100.00 |
| V1 | TOTAL | 106 | 151 | 70.20 | |||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 139.163s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 3121.150s | 3215.317us | 2 | 3 | 66.67 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 292.800s | 239.008us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 95.236s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 95.718s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 107.178s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 86.676s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.530s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.530s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 191.910s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 164.170s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 168.774s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 168.774s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 155.650s | 117.036us | 0 | 3 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 179.290s | 117.038us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 345.970s | 273.026us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 15.770s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 14.964s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 690.590s | 898.493us | 1 | 3 | 33.33 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 324.480s | 248.784us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 636.540s | 541.562us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 636.540s | 541.562us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 15.319s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 275.310s | 164.351us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 275.310s | 164.351us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 436.640s | 2271.438us | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 216.450s | 145.473us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 334.130s | 225.687us | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 206.780s | 147.271us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 240.180s | 161.552us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 197.490s | 145.019us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 236.770s | 165.616us | 0 | 3 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 236.670s | 165.696us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 229.440s | 165.616us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 235.400s | 165.664us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 69.100s | 10.120us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 46.900s | 10.140us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 59.980s | 10.220us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 56.720s | 10.400us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 58.760s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 15.160s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 206.780s | 141.824us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 482.220s | 1779.478us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 53.410s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 48.120s | 10.320us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 58.200s | 10.120us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 50.510s | 10.300us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 60.110s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 51.410s | 10.360us | 0 | 3 | 0.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 15.510s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.568s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 16.509s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 15.798s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 1501.530s | 905.846us | 0 | 100 | 0.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 487.640s | 486.461us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 275.310s | 164.351us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 15.927s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 487.640s | 486.461us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 25.083s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 20.730s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 14.235s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 15.506s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 14.190s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 1501.530s | 905.846us | 0 | 100 | 0.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 345.970s | 273.026us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 524.160s | 375.392us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 376.110s | 267.512us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 424.070s | 289.994us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 216.330s | 144.115us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 1501.530s | 905.846us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 14.673s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 13.831s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 1501.530s | 905.846us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 14.973s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 424.070s | 289.994us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 15.753s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 18.817s | 0.000us | 0 | 90 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 15.402s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 15.341s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 14.610s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 15.610s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 13.831s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 28.664s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 350.170s | 268.132us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 14.032s | 0.000us | 0 | 3 | 0.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 18.617s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 36.210s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 21.698s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation | 356.810s | 268.163us | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 1236.000s | 1266.469us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 14.617s | 0.000us | 0 | 3 | 0.00 | ||
| chip_prim_tl_access | 631.770s | 731.982us | 3 | 3 | 100.00 | ||
| chip_rv_dm_lc_disabled | 690.590s | 898.493us | 1 | 3 | 33.33 | ||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 256.450s | 157.087us | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 46.900s | 10.140us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 239.710s | 145.829us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 206.780s | 147.271us | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 251.640s | 156.391us | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 59.980s | 10.220us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 240.180s | 161.552us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 230.830s | 148.937us | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 273.230s | 172.123us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 58.760s | 10.340us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 356.810s | 268.163us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 39.540s | 10.360us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 362.530s | 215.626us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 197.490s | 145.019us | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 475.230s | 272.380us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 475.230s | 272.380us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 19.402s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 262.480s | 156.815us | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 14.906s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 356.810s | 268.163us | 0 | 3 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 56.720s | 10.400us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 4115.010s | 1464.395us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 69.100s | 10.120us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 334.130s | 225.687us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 334.130s | 225.687us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 334.130s | 225.687us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 507.820s | 264.007us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 1236.000s | 1266.469us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 1236.000s | 1266.469us | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 444.900s | 322.527us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 15.160s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 14.617s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 1501.530s | 905.846us | 0 | 100 | 0.00 |
| chip_sw_data_integrity_escalation | 168.774s | 0.000us | 0 | 6 | 0.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_otbn_mem_scramble | 507.820s | 264.007us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 356.810s | 268.163us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 444.900s | 322.527us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 200.660s | 161.142us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_otbn_mem_scramble | 507.820s | 264.007us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 356.810s | 268.163us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 444.900s | 322.527us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 200.660s | 161.142us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 14.767s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 28.664s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 14.032s | 0.000us | 0 | 3 | 0.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 18.617s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 36.210s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 21.698s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 18.177s | 0.000us | 0 | 15 | 0.00 | ||
| chip_prim_tl_access | 631.770s | 731.982us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 631.770s | 731.982us | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 20.657s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 30.256s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.568s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 69.100s | 10.120us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 46.900s | 10.140us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 59.980s | 10.220us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 56.720s | 10.400us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 58.760s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 15.160s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 206.780s | 141.824us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 206.710s | 143.456us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 206.710s | 143.456us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 195.880s | 138.816us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 215.560s | 136.465us | 0 | 3 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 465.060s | 251.570us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 289.250s | 193.972us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 249.350s | 164.769us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 200.660s | 161.142us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 524.160s | 375.392us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 524.160s | 375.392us | 0 | 3 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 236.720s | 157.096us | 3 | 3 | 100.00 |
| chip_sw_aon_timer_smoketest | 266.130s | 163.244us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 228.580s | 142.942us | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 235.620s | 144.777us | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 239.720s | 174.084us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 306.140s | 182.007us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 294.580s | 171.101us | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 294.780s | 185.393us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 221.990s | 148.041us | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 223.870s | 145.060us | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 308.520s | 248.736us | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 237.010s | 141.618us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 212.350s | 145.500us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 263.980s | 155.768us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 14.025s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 14.460s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 139.163s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 18.863s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 229.310s | 228.422us | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 239.050s | 217.821us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 238.470s | 220.542us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 287.720s | 221.040us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.503s | 0.000us | 0 | 3 | 0.00 |
| chip_rv_dm_lc_disabled | 690.590s | 898.493us | 1 | 3 | 33.33 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 15.499s | 0.000us | 0 | 3 | 0.00 |
| chip_sw_lc_walkthrough_prod | 15.655s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_prodend | 13.757s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_rma | 16.280s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 35.503s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 620.420s | 604.676us | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 633.120s | 578.797us | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 14.686s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 13.175s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 129.589s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 126.441s | 0.000us | 0 | 3 | 0.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 332.140s | 253.290us | 1 | 30 | 3.33 |
| V2 | tl_d_illegal_access | chip_tl_errors | 332.140s | 253.290us | 1 | 30 | 3.33 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 15.700s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 15.560s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 15.700s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 15.560s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 362.930s | 536.825us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 15.520s | 13.908us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 569.670s | 2440.103us | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 667.280s | 2104.428us | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 133.250s | 72.315us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 2210.270s | 11561.075us | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 3312.170s | 14610.498us | 99 | 100 | 99.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 200.490s | 241.159us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 163.860s | 219.726us | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 322.040s | 586.740us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 163.860s | 219.726us | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 494.930s | 872.532us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 3518.220s | 15524.843us | 69 | 100 | 69.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 276.130s | 468.814us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 3457.980s | 5815.189us | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 2221.030s | 4938.026us | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 3229.070s | 5281.778us | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 3520.910s | 6369.586us | 97 | 100 | 97.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 15.900s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 13.794s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 15.302s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 14.474s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 13.533s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 13.190s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 15.045s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 13.356s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 13.939s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 14.950s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 13.850s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 24.610s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 15.103s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 52.783s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 90.268s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 58.645s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 98.227s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 66.001s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 80.243s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 142.700s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 123.822s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 86.702s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 60.984s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 69.343s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 56.351s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 70.825s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 67.179s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 45.025s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 17.161s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 19.803s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 15.454s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 20.265s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 16.132s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 16.977s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 12.244s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 16.772s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 14.693s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 15.202s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 15.437s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 14.071s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 16.128s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 15.106s | 0.000us | 0 | 3 | 0.00 |
| V2 | TOTAL | 1812 | 2405 | 75.34 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 258.640s | 173.661us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 172.460s | 136.925us | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 20.891s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 11.992s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 18.832s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 15.393s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 1501.530s | 905.846us | 0 | 100 | 0.00 |
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 23.939s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 253.540s | 158.276us | 0 | 1 | 0.00 |
| V3 | chip_sw_coremark | chip_sw_coremark | 14.895s | 0.000us | 0 | 1 | 0.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 15.355s | 0.000us | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 20.891s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 11.992s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 18.832s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 12.811s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 16.156s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 16.616s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 13.414s | 0.000us | 0 | 3 | 0.00 |
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 1377.920s | 905.678us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_kat_test | 207.530s | 144.308us | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 197.880s | 141.636us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_0 | 590.090s | 346.757us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_10 | 550.340s | 302.195us | 3 | 3 | 100.00 | ||
| chip_sw_dma_inline_hashing | 256.060s | 188.426us | 3 | 3 | 100.00 | ||
| chip_sw_dma_abort | 276.770s | 192.895us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 12.992s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 15.780s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 14.731s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 14.975s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 15.044s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 14.740s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 17.281s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 13.970s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 14.380s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 13.897s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 303.020s | 187.196us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 524.140s | 334.239us | 3 | 3 | 100.00 | ||
| TOTAL | 1945 | 2639 | 73.70 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 72.88 | 72.26 | 79.52 | 63.73 | 57.14 | 80.22 | 68.24 | 89.05 |
Job returned non-zero exit code has 411 failures:
0.chip_sw_example_manufacturer.101661918332606530897932656400083040254363241709769061918507506564059722886384
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 152.879s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_manufacturer.6636349494883511167966814715481428078770918305818920798099632713440485394996
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 26.256s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_data_integrity_escalation.14969774411452470037963027208042451778575245512933933599612991117787862680089
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 154.579s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_data_integrity_escalation.35514398240642579455904451864430790663590206494366980078864476672956323086294
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 18.265s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 4 more failures.
0.chip_sw_sleep_pin_wake.104570876509925979022628702173925150338000390282885424314553812872251750565913
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 176.732s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_wake.8950068406939795406954449677928600568267477144966196054727677739073369069702
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 22.730s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_sleep_pin_retention.96792264694254753383071268175700507661555063687678172477278314626158116925072
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 149.239s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_retention.55728363501572411075246072508565202214911214933627380270886484634283033409279
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log
Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 16.629s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_uart_tx_rx.69005939232557618640713627712721668735701045852692004751790776819667489892893
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 166.144s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_uart_tx_rx.15670437102512343924034159236160420242556736331232381191720006796302257349401
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 26.244s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 94 failures:
0.chip_sw_all_escalation_resets.115685718694371003515969928689378453548794265126016713927514172007029360272329
Line 516, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.611000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.611000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_all_escalation_resets.73656968142417823787880144725192109768889826418383792122434871554956088524695
Line 508, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.738000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.738000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 89 more failures.
0.chip_sw_rstmgr_rst_cnsty_escalation.99723113679474099149419175255365559509496454750331821381786749713995796745235
Line 473, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.690000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.690000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_rst_cnsty_escalation.56520617220259123806086050235120391598112004884480952931761375997214822598495
Line 515, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.678000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.678000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 36 failures:
Test xbar_access_same_device_slow_rsp has 31 failures.
2.xbar_access_same_device_slow_rsp.46236442885796743703296023773306425704328959276163003082365245487917251646452
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
4.xbar_access_same_device_slow_rsp.109983725458528475426501262427708580192706493550740947940617410977545726165431
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
... and 29 more failures.
Test xbar_stress_all_with_reset_error has 3 failures.
11.xbar_stress_all_with_reset_error.93877898693833056009704486437492526112806921067544203687873918537542741704648
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
26.xbar_stress_all_with_reset_error.55311918413615617825520395373428929533510143378085766653070532387796036191324
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test xbar_random_slow_rsp has 1 failures.
70.xbar_random_slow_rsp.24173409174596347146723547200687700364163741914467831355552150736466696506309
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/70.xbar_random_slow_rsp/latest/run.log
Job timed out after 60 minutes
Test chip_sw_spi_device_pass_through has 1 failures.
0.chip_sw_spi_device_pass_through.37620179704707243791539292780922352148323967015598816427088481420754678573031
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
Job timed out after 60 minutes
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 33 failures:
0.chip_sw_otbn_ecdsa_op_irq_jitter_en.11311636582816826314733975331289388339493986790232010648909903963195326387044
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otbn_ecdsa_op_irq_jitter_en.8371053193728119666864263330507345552328219601358075363106049988339220991532
Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_aes_enc_jitter_en.112289001030729890707022731745271998757311831459232598641303769565316683495957
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aes_enc_jitter_en.60593003517603620833300628642008810154640148191402720746305497938348183628964
Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_hmac_enc_jitter_en.113075942120545878055567617603487793307144833176294163002660511769054744389801
Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_hmac_enc_jitter_en.113546070880289618595376206663823121928871239192884447990414413576035462460495
Line 439, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.107535434319374286521921198459082446798846144236783782701026238115858136344545
Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_jitter_en.82881989029766322778652734315767080785982662811103752179811224631835074568699
Line 456, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_kmac_mode_kmac_jitter_en.73048255279069936702407558743057584831119008417257461222556891920882753055009
Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_mode_kmac_jitter_en.77370737078457612033078888909513482295463259431295808327545188742799209270200
Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 27 failures:
0.chip_tl_errors.85287460733954062248692234317094633215740893898458753775471340869508535721216
Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.052000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_tl_errors.105631306395859231898365752754958779533747583040168995277512350919519600464011
Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.065000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.065000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 18 failures:
0.chip_sw_rstmgr_cpu_info.86133476565115054883519757822811841199813248179838632558252624219427803226230
Line 481, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.392000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_cpu_info.38875366690720151939433952699959849672432938842011648557590766450124305204490
Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.456000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.456000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_soc_proxy_smoketest.63525191132706389645881652227747044579829041947711198712292357462835816284814
Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
UVM_ERROR @ 143.424000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 143.424000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_smoketest.83929866626303274473587769881680322560242079671187252781028553453788747230405
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log
Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
UVM_ERROR @ 143.552000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 143.552000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_aes_trans.26053474143206133633613158032063132514594600074577987583492524227723706933956
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_aes_trans.19832311508008542077442769484423444015293252537921754084638265749563166522110
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_hmac_trans.88181646598487385830538721201063124044026874085603270973557522149957329026377
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_hmac_trans.97020329392945300322237712693806602687978385266781058430012772054492737628349
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.696000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_kmac_trans.61120452053161528519856770287453734911076821063024909069735988521894232677664
Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_kmac_trans.62553145199535674767520109334600925243975986705534828242546148720405423723010
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.86980978123830851774531938764188804497826571331150827055048365066474025925730
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.23251091797397566458053182825267398440601334993295584624003415390864492497264
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
0.chip_csr_bit_bash.62675500360273139616620953328909824447369512293171002944408134077344676093253
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_bit_bash.64198819885306645976851878563261698394056333547960805793783890261648510002285
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_csr_aliasing.87536255699154354128085121090596038714935013834919950013274589312070064037813
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_aliasing.96234367995780116757672658154810246489246909057489325252040836486985973424109
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_same_csr_outstanding.89052426898445816945080148074111916436096574561506863833689960172431218163834
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_same_csr_outstanding.43913314207968890607206235632511411979282744299780254057522226696928711537364
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:
0.chip_sw_keymgr_dpe_key_derivation.115178942171365935374418337958782965930450279686211645317795674185789103463863
Line 456, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 268.036000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11564880684712539970969602291401349880500799433989858657078343806271027638923214249676440589639138824492140289989289049433247686620702535358219929600220252 [0xdccff592aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35a9945637f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation.54756406615246015877927404552377065191854141019178927715677373927762758251637
Line 441, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 268.124000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1641064371068005622058231463861982834037135047869037825077476869921478440565074580033686950939440440421607568346194893799160316806890397792537986891865180 [0x1f555b05aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39903ebf47f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.124000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.60887833762484939945602269180456447575614704822345100069624970106047483976411
Line 430, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 268.000000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12239601892963118562982074371569645381828864933618311496970016469656506389441355460134649602153693599090302751385578585541852346849730946681214044916243548 [0xe9b1ed86aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd36fe75d777f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_prod.102870953684767344443152251186676981555752568874143802701203340598545408888329
Line 462, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 268.132000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2298878410814219872580989241527121861968073848107285310429048050213770311147161113593781868536835248017194063361035730023747353176465147912274579772759132 [0x2be4af00aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3adb21ff17f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.132000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:
0.chip_jtag_csr_rw.111994945240585945491831097949418077760322372556120032394958183207224700573645
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.012000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000 a_data: 'he859eb8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h1 a_user: 'h248ca d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.012000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_csr_rw.102849504799405966072347947471649497584339396159005417862719974312594706076025
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.036000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000 a_data: 'h275e8edb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h1 a_user: 'h248df d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_jtag_mem_access.38775643470224626228251222100827869709372773530289912376505703682128373114261
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.038000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000 a_data: 'h754ddd7b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h0 a_user: 'h2695c d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.038000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_mem_access.9302155664391896403944711453766083499212770263997558815004201629451363947518
Line 5960, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.018000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42094) { a_addr: 'h30480000 a_data: 'h7b9703e2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h1 a_user: 'h2489e d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.018000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 5 failures:
Test chip_sw_otp_ctrl_escalation has 1 failures.
0.chip_sw_otp_ctrl_escalation.35552731771885218702606467815822935936497444865278106030473856912475218838884
Line 465, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.276000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.276000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_all_escalation_resets has 4 failures.
5.chip_sw_all_escalation_resets.27159866625835447348079781661315252543878288877915272780590835398518450042688
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.104000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.104000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.chip_sw_all_escalation_resets.4482260006271474906376819843165639258208136820029506083826791091335498689074
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.068000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
0.chip_sw_example_rom.65768434212072950969042436794604148179214483696352802616283606174427786344296
Line 595, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_example_rom.108353690278101892296297734749781794947796453249434512189450080596161574578033
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
0.chip_sw_spi_device_pass_through_collision.28548310115837063306961433254648638067494754138002783622904465494005683956841
Line 485, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 239.008000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 239.008000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_spi_device_pass_through_collision.73924701753746832456994647024089205000532334387478362292691812295868627833151
Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 170.904000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 170.904000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 3 failures:
0.chip_sw_rstmgr_alert_info.49930168494144226541823111341853266397571446736934327794657647702920212995424
Line 491, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 290.141000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 290.141000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_alert_info.54298779621191736506965705284047502040167850041397915802166708080413474184265
Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 289.994000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 289.994000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
0.chip_sw_soc_proxy_external_wakeup.80045988756920007831770421633830616829734362729195580588927477421430431683720
Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.803000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.803000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_external_wakeup.27998621560107570021772792383212926060061447432938443268385873940306031672912
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.791000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.791000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 3 failures:
0.chip_sw_soc_proxy_gpios.69049832287488311806823576522209049156463409426018418897801429848208910885987
Line 437, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.465000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.465000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_gpios.108714110362429417503225914804075196477142964714419464151558356030178311749923
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.505000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.505000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 3 failures:
0.chip_sw_aon_timer_irq.16760849479669510982653822136407413955749857418507706482819261197600890952035
Line 427, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 600.494000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4616 usec which is not in the range 421 usec and 480 usec
UVM_INFO @ 600.494000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_irq.56690645394090305169834749827750100871240980113481018052356488950706904664518
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 543.518000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4022 usec which is not in the range 367 usec and 420 usec
UVM_INFO @ 543.518000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
0.chip_sw_aon_timer_wdog_bite_reset.27635408819051621345042133979807821688329592883062631395144731972655912159561
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.351000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.351000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_wdog_bite_reset.78841286461972910452614949688309785111790348174160958406669540235950959745778
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.292000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.292000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
0.chip_sw_rv_core_ibex_nmi_irq.70226937557238999988293582288022355605234360617857127506505362968647629965604
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.570000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.570000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_nmi_irq.9730875495288626624008146973822571299591245414437356274758107687870320900129
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.583000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.583000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
0.chip_sw_kmac_app_rom.23684690399875052382125379040181760117609763212001993407344980747199279056833
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_app_rom.16744661960189543583685913739736340914187347378914858067947205861534296980609
Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 2 failures:
0.chip_sw_dma_abort.45749976020443555754060137210875651690522116999819449378812562937520637866620
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_FATAL @ 162.404000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 162.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_dma_abort.8976188566026893958578882842950860545720239826198540717099920187518574517705
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log
UVM_FATAL @ 166.968000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 166.968000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 2 failures:
37.chip_sw_all_escalation_resets.115025207657181522516671360575085381285973120335505020111495744668495487930217
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.340001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.chip_sw_all_escalation_resets.112840072695681917563144398994745045791592320810281950028783843850623994143246
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.160001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
44.chip_sw_all_escalation_resets.70144061037954011942977226998353325900939845517639490556685571762268817713428
Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.821000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.821000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
84.chip_sw_all_escalation_resets.91608671619915657714634242176680573083357055766858101364359036987559885333496
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.780000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:
1.chip_rv_dm_lc_disabled.46551452452828786446688212908683217201701691931519472232245944733260320425831
Line 216, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 129.378000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406fc read out mismatch
UVM_INFO @ 129.378000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_rv_dm_lc_disabled.61728746313633072645116135291840795631371811329033761908394257250801030503588
Line 258, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 775.130000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x4077c read out mismatch
UVM_INFO @ 775.130000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 1 failures:
2.chip_sw_dma_abort.58128014099445556967334796726935173467822114647209802572711732919965219672380
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 192.895000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 192.895000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 1 failures:
39.chip_sw_all_escalation_resets.102804023344989025254226213847754573254530007178081236985810711741638209561792
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 160.212000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 160.212000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31913) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.chip_tl_errors.80722718980268456913105877763139922018087248234638244254696362391728323988411
Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log
UVM_ERROR @ 117.699000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31913) { a_addr: 'h40408 a_data: 'hcf73b49f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h1a65f d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.699000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32001) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.chip_tl_errors.3808657332945467027264709088896899541262953441343860199765949355105763002250
Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_tl_errors/latest/run.log
UVM_ERROR @ 118.027000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32001) { a_addr: 'h40768 a_data: 'h6da616e4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h19a58 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 118.027000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---