AES/MASKED Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	69.958us	2	2	100.00
V1	smoke	aes_smoke	7.000s	212.896us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	62.558us	10	10	100.00
V1	csr_rw	aes_csr_rw	3.000s	157.560us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	803.362us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1572.777us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	79.566us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	157.560us	40	40	100.00
		aes_csr_aliasing	5.000s	1572.777us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	7.000s	212.896us	100	100	100.00
		aes_config_error	11.000s	883.473us	100	100	100.00
		aes_stress	21.000s	6674.136us	100	100	100.00
V2	key_length	aes_smoke	7.000s	212.896us	100	100	100.00
		aes_config_error	11.000s	883.473us	100	100	100.00
		aes_stress	21.000s	6674.136us	100	100	100.00
V2	back2back	aes_stress	21.000s	6674.136us	100	100	100.00
		aes_b2b	30.000s	806.328us	100	100	100.00
V2	backpressure	aes_stress	21.000s	6674.136us	100	100	100.00
V2	multi_message	aes_smoke	7.000s	212.896us	100	100	100.00
		aes_config_error	11.000s	883.473us	100	100	100.00
		aes_stress	21.000s	6674.136us	100	100	100.00
		aes_alert_reset	10.000s	277.292us	100	100	100.00
V2	failure_test	aes_man_cfg_err	6.000s	140.004us	100	100	100.00
		aes_config_error	11.000s	883.473us	100	100	100.00
		aes_alert_reset	10.000s	277.292us	100	100	100.00
V2	trigger_clear_test	aes_clear	42.000s	2956.393us	99	100	99.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	110.106us	2	2	100.00
V2	reset_recovery	aes_alert_reset	10.000s	277.292us	100	100	100.00
V2	stress	aes_stress	21.000s	6674.136us	100	100	100.00
V2	sideload	aes_stress	21.000s	6674.136us	100	100	100.00
		aes_sideload	11.000s	1883.070us	100	100	100.00
V2	deinitialization	aes_deinit	9.000s	4490.230us	100	100	100.00
V2	stress_all	aes_stress_all	437.000s	10091.659us	19	20	95.00
V2	alert_test	aes_alert_test	5.000s	98.158us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	171.053us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	171.053us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	62.558us	10	10	100.00
		aes_csr_rw	3.000s	157.560us	40	40	100.00
		aes_csr_aliasing	5.000s	1572.777us	10	10	100.00
		aes_same_csr_outstanding	3.000s	229.505us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	62.558us	10	10	100.00
		aes_csr_rw	3.000s	157.560us	40	40	100.00
		aes_csr_aliasing	5.000s	1572.777us	10	10	100.00
		aes_same_csr_outstanding	3.000s	229.505us	40	40	100.00
V2		TOTAL			1000	1002	99.80
V2S	reseeding	aes_reseed	21.000s	947.141us	100	100	100.00
V2S	fault_inject	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	289.823us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	289.823us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	289.823us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	289.823us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	584.323us	40	40	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1511.816us	10	10	100.00
		aes_tl_intg_err	4.000s	437.852us	40	40	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	437.852us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	277.292us	100	100	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	289.823us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	212.896us	100	100	100.00
		aes_stress	21.000s	6674.136us	100	100	100.00
		aes_alert_reset	10.000s	277.292us	100	100	100.00
		aes_core_fi	69.000s	10044.587us	134	140	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	289.823us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	62.736us	100	100	100.00
		aes_stress	21.000s	6674.136us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	21.000s	6674.136us	100	100	100.00
		aes_sideload	11.000s	1883.070us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	62.736us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	62.736us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	62.736us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	62.736us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	62.736us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	21.000s	6674.136us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	21.000s	6674.136us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	680.059us	97	100	97.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
		aes_ctr_fi	6.000s	88.177us	100	100	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	680.059us	97	100	97.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10006.016us	667	700	95.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	680.059us	97	100	97.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_ctr_fi	6.000s	88.177us	100	100	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
		aes_ctr_fi	6.000s	88.177us	100	100	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	277.292us	100	100	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
		aes_ctr_fi	6.000s	88.177us	100	100	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
		aes_ctr_fi	6.000s	88.177us	100	100	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_ctr_fi	6.000s	88.177us	100	100	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	680.059us	97	100	97.00
		aes_control_fi	58.000s	10016.333us	554	600	92.33
		aes_cipher_fi	50.000s	10006.016us	667	700	95.29
V2S		TOTAL			1882	1970	95.53
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	41.000s	692.918us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3094	3204	96.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.62	96.50	99.43	95.35	97.99	97.78	98.51	97.79

Failure Buckets

Job timed out after * minutes has 44 failures:
- Test aes_control_fi has 31 failures.
  - 4.aes_control_fi.106737818828941824358392181380633552021023861565891260357311916137562898876479
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_control_fi.58783919018540254183042504887675691463537484800829376229214622890509093401549
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 29 more failures.
- Test aes_cipher_fi has 13 failures.
  - 14.aes_cipher_fi.100272145382276423921331447706328210239114095284677330679704260862751854514839
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_cipher_fi.43593416342515123672160350335802930775805306638781321141999197107567496197484
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 20 failures:
- Test aes_cipher_fi has 20 failures.
  - 15.aes_cipher_fi.84680507894139506813137329473768120402768041524317279084620313703343765794272
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005690616 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005690616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.aes_cipher_fi.56264508970221407986535742608304783204387908674709471551994805408447819735934
    Line 149, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10059807319 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10059807319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 15.aes_control_fi.565475534570271199270363050736735972102221422171352637706374349423641940504
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019861023 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019861023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 67.aes_control_fi.58151173919150069288681104419839353587297294081632077272078786842104079259033
    Line 130, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/67.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016667134 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016667134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 12 failures:

Test aes_stress_all_with_rand_reset has 12 failures.

0.aes_stress_all_with_rand_reset.70303673265538242567241662759733378774504742897165458512352802326274102109726
Line 1212, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1314309355 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1314309355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.66409105542215918549768258171292194497728316143482111264448982043175984575584
Line 1144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1353509882 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1353509882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 5.aes_stress_all_with_rand_reset.78409185899842597258705103492096311001122704884721908119674609140353263836397
    Line 161, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  60652020 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  60652020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.6973956807387680544583188911540005592267175624052664467939193580975204453738
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  41741230 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  41741230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 3.aes_core_fi.113399754141839923976912158114466145731592978032076272918466523069285074479726
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020155341 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020155341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.aes_core_fi.104385591020801198494583616031851687655614396868673498327984509522827511654783
    Line 135, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011407002 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011407002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 15.aes_core_fi.84666686792179776784752777005602837982978701673509122299253033585454423439863
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036883218 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036883218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 69.aes_core_fi.1582271262892388430128952411528668605365881589934212248265107418056270322932
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/69.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012031935 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012031935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 7.aes_stress_all_with_rand_reset.15806473030776861001249716202922139392438085901583409021073947279658252104646
    Line 182, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209321621 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 209321621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.110458050362802730022516573438485100541218219051065936520025590659563850567306
    Line 316, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 329846388 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 329846388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 7.aes_clear.105230200202255851212499054528481189383991585577120257507547943636592610565844
    Line 4566, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_clear/latest/run.log
```
  UVM_FATAL @  27099184 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 1
           TEST FAILED MESSAGES DID NOT MATCH

                 0 a6 	 e2 	 65 	 0
                 1 bc 	 41 	 9b 	 0
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=31) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.93453517855908051428091161649680214772442931222142778938615249163433898389195
    Line 3893356, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 10091659108 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x695e1c84, Comparison=CompareOpEq, exp_data=0x1, call_count=31)
  UVM_INFO @ 10091659108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 24.aes_core_fi.111805286981384466187408401421218905094506681150023222821139262650710317033406
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10044587438 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xcbf8a584, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10044587438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

42.aes_fi.84771386002195023028123462785342677661903178293623663531622016278572826899090
Line 2614, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/42.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 50373963 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 50307296 PS)
  UVM_ERROR @  50373963 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  50373963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.90067802009042573034278688433820453588121376114968857558047705861925320397995
    Line 406, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1199389210 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1199389210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

8.aes_fi.89052785292421482979461325642880940816950043985244945671771755048483391150154
Line 3563, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9738817 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9728400 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 9738817 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9728400 PS)
  UVM_ERROR @   9738817 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.24562910647505674717217612090803037039541471159036485648140848893310863929269
    Line 500, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7025599442 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 7025599442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

10.aes_fi.84153698485529291269984606557399501655578610460076451384451740057015003145383
Line 3133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/10.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 21296409 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 21275576 PS)
  UVM_ERROR @  21296409 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  21296409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---