CSRNG Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	4.000s	71.649us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	26.148us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	65.220us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	2539.367us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	165.913us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	43.941us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	65.220us	20	20	100.00
		csrng_csr_aliasing	5.000s	165.913us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	1031.962us	200	200	100.00
V2	alerts	csrng_alert	53.000s	4840.664us	500	500	100.00
V2	err	csrng_err	4.000s	81.214us	500	500	100.00
V2	cmds	csrng_cmds	328.000s	15952.478us	49	50	98.00
V2	life cycle	csrng_cmds	328.000s	15952.478us	49	50	98.00
V2	stress_all	csrng_stress_all	888.000s	66264.296us	46	50	92.00
V2	intr_test	csrng_intr_test	3.000s	41.785us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	207.366us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	717.724us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	717.724us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	26.148us	5	5	100.00
		csrng_csr_rw	3.000s	65.220us	20	20	100.00
		csrng_csr_aliasing	5.000s	165.913us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	723.095us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	26.148us	5	5	100.00
		csrng_csr_rw	3.000s	65.220us	20	20	100.00
		csrng_csr_aliasing	5.000s	165.913us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	723.095us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_tl_intg_err	14.000s	428.614us	20	20	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_config_regwen	csrng_csr_rw	3.000s	65.220us	20	20	100.00
		csrng_regwen	4.000s	120.342us	50	50	100.00
V2S	sec_cm_config_mubi	csrng_alert	53.000s	4840.664us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	888.000s	66264.296us	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	53.000s	4840.664us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	888.000s	66264.296us	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	53.000s	4840.664us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	428.614us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
		csrng_sec_cm	7.000s	877.100us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	1031.962us	200	200	100.00
		csrng_err	4.000s	81.214us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	445.000s	25033.873us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1625	1630	99.69

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.64	98.87	97.25	99.91	96.76	92.08	100.00	95.40	90.22

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
  • Test csrng_stress_all has 4 failures.

    • 17.csrng_stress_all.50695403601383068803558297227047547208784131912130359574336265657175132144047
      Line 173, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log

        UVM_ERROR @ 19352622555 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 19352622555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 29.csrng_stress_all.23345378070598969909841548631884064505655871801382547537404694643220073485198
      Line 155, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log

        UVM_ERROR @ 2697814246 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 2697814246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Job timed out after * minutes has 1 failures:
  • Test csrng_cmds has 1 failures.

    • 13.csrng_cmds.88580105419284411935804894025624578163516997295384969600841731922031722566327
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/13.csrng_cmds/latest/run.log

        Job timed out after 60 minutes