DMA Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	34.000s	279.875us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	35.000s	347.590us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	34.000s	328.416us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	67.487us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	35.007us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	14.000s	446.597us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	305.295us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	87.766us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	35.007us	20	20	100.00
		dma_csr_aliasing	7.000s	305.295us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	129.000s	6019.711us	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	1403.000s	110264.572us	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	475.000s	34366.346us	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	475.000s	34366.346us	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	1403.000s	110264.572us	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	859.000s	57527.177us	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	475.000s	34366.346us	3	3	100.00
V2	dma_abort	dma_abort	43.000s	3059.360us	5	5	100.00
V2	dma_stress_all	dma_stress_all	278.000s	32334.844us	3	3	100.00
V2	alert_test	dma_alert_test	29.000s	24.278us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	16.023us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	511.122us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	511.122us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	67.487us	5	5	100.00
		dma_csr_rw	2.000s	35.007us	20	20	100.00
		dma_csr_aliasing	7.000s	305.295us	5	5	100.00
		dma_same_csr_outstanding	4.000s	374.534us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	67.487us	5	5	100.00
		dma_csr_rw	2.000s	35.007us	20	20	100.00
		dma_csr_aliasing	7.000s	305.295us	5	5	100.00
		dma_same_csr_outstanding	4.000s	374.534us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	52.000s	262.214us	5	5	100.00
		dma_generic_stress	859.000s	57527.177us	5	5	100.00
		dma_handshake_stress	475.000s	34366.346us	3	3	100.00
V2S	dma_config_lock	dma_config_lock	39.000s	334.262us	15	15	100.00
V2S	tl_intg_err	dma_sec_cm	29.000s	10.885us	5	5	100.00
		dma_tl_intg_err	5.000s	184.741us	20	20	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	157.000s	48336.353us	25	25	100.00
		dma_longer_transfer	34.000s	438.493us	5	5	100.00
		dma_stress_all_with_rand_reset	35.000s	400.794us	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.31	97.38	95.83	96.89	96.04	83.12	92.96	95.97	79.35

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.38673830716094610867072337286479411360407314702212558626411021623607133213274
      Line 103, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  400793524ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  400793524ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---