EDN Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.230s	18.741us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	18.179us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.970s	12.929us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.550s	516.110us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.540s	148.489us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.520s	167.238us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.970s	12.929us	20	20	100.00
		edn_csr_aliasing	1.540s	148.489us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	5.600s	651.770us	300	300	100.00
V2	csrng_commands	edn_genbits	5.600s	651.770us	300	300	100.00
V2	genbits	edn_genbits	5.600s	651.770us	300	300	100.00
V2	interrupts	edn_intr	1.390s	20.812us	50	50	100.00
V2	alerts	edn_alert	1.590s	173.625us	200	200	100.00
V2	errs	edn_err	1.540s	30.536us	100	100	100.00
V2	disable	edn_disable	1.150s	42.512us	50	50	100.00
		edn_disable_auto_req_mode	1.490s	49.025us	50	50	100.00
V2	stress_all	edn_stress_all	5.420s	3042.812us	50	50	100.00
V2	intr_test	edn_intr_test	1.030s	16.139us	50	50	100.00
V2	alert_test	edn_alert_test	1.110s	19.829us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.850s	271.261us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.850s	271.261us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	18.179us	5	5	100.00
		edn_csr_rw	0.970s	12.929us	20	20	100.00
		edn_csr_aliasing	1.540s	148.489us	5	5	100.00
		edn_same_csr_outstanding	1.200s	148.821us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	18.179us	5	5	100.00
		edn_csr_rw	0.970s	12.929us	20	20	100.00
		edn_csr_aliasing	1.540s	148.489us	5	5	100.00
		edn_same_csr_outstanding	1.200s	148.821us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_tl_intg_err	2.800s	187.598us	20	20	100.00
		edn_sec_cm	6.230s	1576.815us	5	5	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.030s	18.067us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.590s	173.625us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.230s	1576.815us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.230s	1576.815us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.230s	1576.815us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.230s	1576.815us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.590s	173.625us	200	200	100.00
		edn_sec_cm	6.230s	1576.815us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.590s	173.625us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.800s	187.598us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	10207.530s	10000000.000us	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1113	1130	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	98.87	94.23	97.07	92.44	96.33	97.56	93.13

Failure Buckets

• Job timed out after * minutes has 16 failures:
  • Test edn_stress_all_with_rand_reset has 16 failures.

    • 0.edn_stress_all_with_rand_reset.77652693441552468921312671776694885358437205501443601115109539974914722767965
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 1.edn_stress_all_with_rand_reset.83740916693025223052100154552381502331288774257656900053776952710311139401544
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 14 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 41.edn_stress_all_with_rand_reset.36041965435451852144557668041270090421136231582115204200881247528691525463813
      Line 204, in log /nightly/current_run/scratch/master/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---