HMAC Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.430s	3340.716us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.300s	162.263us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.320s	193.601us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.440s	2112.907us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.140s	539.066us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	846.630s	100790.629us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.320s	193.601us	20	20	100.00
		hmac_csr_aliasing	9.140s	539.066us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	107.080s	33848.976us	10	10	100.00
V2	back_pressure	hmac_back_pressure	91.200s	1750.996us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	291.130s	6416.356us	30	30	100.00
		hmac_test_sha384_vectors	505.190s	28858.924us	75	75	100.00
		hmac_test_sha512_vectors	536.400s	65145.723us	75	75	100.00
		hmac_test_hmac256_vectors	15.520s	2026.576us	50	50	100.00
		hmac_test_hmac384_vectors	19.770s	1727.893us	60	60	100.00
		hmac_test_hmac512_vectors	18.980s	362.211us	75	75	100.00
V2	burst_wr	hmac_burst_wr	35.570s	7357.911us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	864.050s	4819.884us	10	10	100.00
V2	error	hmac_error	126.060s	16360.288us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	87.610s	6209.930us	10	10	100.00
V2	save_and_restore	hmac_smoke	14.430s	3340.716us	10	10	100.00
		hmac_long_msg	107.080s	33848.976us	10	10	100.00
		hmac_back_pressure	91.200s	1750.996us	25	25	100.00
		hmac_datapath_stress	864.050s	4819.884us	10	10	100.00
		hmac_burst_wr	35.570s	7357.911us	50	50	100.00
		hmac_stress_all	2070.790s	66419.868us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.430s	3340.716us	10	10	100.00
		hmac_long_msg	107.080s	33848.976us	10	10	100.00
		hmac_back_pressure	91.200s	1750.996us	25	25	100.00
		hmac_datapath_stress	864.050s	4819.884us	10	10	100.00
		hmac_wipe_secret	87.610s	6209.930us	10	10	100.00
		hmac_test_sha256_vectors	291.130s	6416.356us	30	30	100.00
		hmac_test_sha384_vectors	505.190s	28858.924us	75	75	100.00
		hmac_test_sha512_vectors	536.400s	65145.723us	75	75	100.00
		hmac_test_hmac256_vectors	15.520s	2026.576us	50	50	100.00
		hmac_test_hmac384_vectors	19.770s	1727.893us	60	60	100.00
		hmac_test_hmac512_vectors	18.980s	362.211us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.430s	3340.716us	10	10	100.00
		hmac_long_msg	107.080s	33848.976us	10	10	100.00
		hmac_back_pressure	91.200s	1750.996us	25	25	100.00
		hmac_datapath_stress	864.050s	4819.884us	10	10	100.00
		hmac_burst_wr	35.570s	7357.911us	50	50	100.00
		hmac_error	126.060s	16360.288us	10	10	100.00
		hmac_wipe_secret	87.610s	6209.930us	10	10	100.00
		hmac_test_sha256_vectors	291.130s	6416.356us	30	30	100.00
		hmac_test_sha384_vectors	505.190s	28858.924us	75	75	100.00
		hmac_test_sha512_vectors	536.400s	65145.723us	75	75	100.00
		hmac_test_hmac256_vectors	15.520s	2026.576us	50	50	100.00
		hmac_test_hmac384_vectors	19.770s	1727.893us	60	60	100.00
		hmac_test_hmac512_vectors	18.980s	362.211us	75	75	100.00
		hmac_stress_all	2070.790s	66419.868us	50	50	100.00
V2	stress_all	hmac_stress_all	2070.790s	66419.868us	50	50	100.00
V2	alert_test	hmac_alert_test	0.960s	41.573us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	73.374us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.280s	857.312us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.280s	857.312us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.300s	162.263us	5	5	100.00
		hmac_csr_rw	1.320s	193.601us	20	20	100.00
		hmac_csr_aliasing	9.140s	539.066us	5	5	100.00
		hmac_same_csr_outstanding	2.860s	103.352us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.300s	162.263us	5	5	100.00
		hmac_csr_rw	1.320s	193.601us	20	20	100.00
		hmac_csr_aliasing	9.140s	539.066us	5	5	100.00
		hmac_same_csr_outstanding	2.860s	103.352us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.720s	264.392us	5	5	100.00
		hmac_tl_intg_err	4.920s	287.050us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.920s	287.050us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.430s	3340.716us	10	10	100.00
V3	stress_reset	hmac_stress_reset	5.020s	202.531us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	317.370s	9581.429us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.350s	29.275us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.16	99.95	96.80	100.00	100.00	99.83	97.61	99.95