KEYMGR Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.100s	1575.307us	50	50	100.00
V1	random	keymgr_random	66.440s	9032.996us	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.710s	234.866us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.830s	57.378us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	26.000s	1297.948us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.640s	1828.673us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.080s	53.828us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.830s	57.378us	20	20	100.00
		keymgr_csr_aliasing	10.640s	1828.673us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	95.230s	2298.377us	50	50	100.00
V2	sideload	keymgr_sideload	50.300s	6370.018us	50	50	100.00
		keymgr_sideload_kmac	35.450s	1622.885us	50	50	100.00
		keymgr_sideload_aes	51.810s	13223.987us	50	50	100.00
		keymgr_sideload_otbn	21.590s	3970.114us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.810s	2089.321us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	10.420s	781.578us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.050s	1187.861us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	55.840s	12793.598us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	59.050s	6988.711us	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	8.200s	1445.357us	49	50	98.00
V2	stress_all	keymgr_stress_all	181.740s	14154.286us	49	50	98.00
V2	intr_test	keymgr_intr_test	1.200s	11.042us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.310s	26.881us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.350s	462.549us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.350s	462.549us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.710s	234.866us	5	5	100.00
		keymgr_csr_rw	1.830s	57.378us	20	20	100.00
		keymgr_csr_aliasing	10.640s	1828.673us	5	5	100.00
		keymgr_same_csr_outstanding	4.680s	331.106us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.710s	234.866us	5	5	100.00
		keymgr_csr_rw	1.830s	57.378us	20	20	100.00
		keymgr_csr_aliasing	10.640s	1828.673us	5	5	100.00
		keymgr_same_csr_outstanding	4.680s	331.106us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	tl_intg_err	keymgr_tl_intg_err	9.610s	281.603us	20	20	100.00
		keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.860s	285.463us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.860s	285.463us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.860s	285.463us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.860s	285.463us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.780s	576.084us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.610s	281.603us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.860s	285.463us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	95.230s	2298.377us	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_csr_rw	1.830s	57.378us	20	20	100.00
		keymgr_random	66.440s	9032.996us	49	50	98.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_csr_rw	1.830s	57.378us	20	20	100.00
		keymgr_random	66.440s	9032.996us	49	50	98.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_csr_rw	1.830s	57.378us	20	20	100.00
		keymgr_random	66.440s	9032.996us	49	50	98.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	10.420s	781.578us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	59.050s	6988.711us	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	59.050s	6988.711us	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	66.440s	9032.996us	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	18.700s	1293.226us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	8.780s	623.868us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	10.420s	781.578us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	8.780s	623.868us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	8.780s	623.868us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	8.780s	623.868us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.180s	2308.007us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	8.780s	623.868us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.840s	2737.985us	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1081	1110	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.13	98.15	98.62	100.00	99.01	97.72	91.09

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test keymgr_stress_all_with_rand_reset has 23 failures.

    • 1.keymgr_stress_all_with_rand_reset.1974782962162422625794438616542924392462729246385585919278125720169254217026
      Line 909, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4382797624 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4382797624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.keymgr_stress_all_with_rand_reset.37763211792735848076345947273189087586845756037854316439995589250616187445022
      Line 248, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 205982618 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 205982618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_random has 1 failures.

    • 44.keymgr_random.14856589462055508863409175044415962862370725792092278252754068204892417991736
      Line 152, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_random/latest/run.log

        UVM_ERROR @   6562775 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @   6562775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 44.keymgr_hwsw_invalid_input.85434240467995778344507005149781192637419673759187386448982811778960625345474
      Line 700, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest/run.log

        UVM_ERROR @  82587952 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  82587952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 47.keymgr_stress_all.45818433468406657693895668882071069291683781836729623433059393743574870929132
      Line 541, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 195238427 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 195238427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 22.keymgr_stress_all_with_rand_reset.81316506027269746108689530049914217172229969751502957900788003630836700877209
      Line 823, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 268108053 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 268108053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:

  • Test keymgr_sync_async_fault_cross has 1 failures.

    • 25.keymgr_sync_async_fault_cross.61900504111834160094004153660478029481954752764897828162395605044266728305079
      Line 183, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest/run.log

        UVM_ERROR @  65151714 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @  65151714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 40.keymgr_stress_all_with_rand_reset.2259320698028681503883699119827751787016336673491606601324221170653743185922
      Line 847, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 147260122 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
        UVM_INFO @ 147260122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---