KEYMGR_DPE Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	274.150s	14988.490us	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.340s	37.136us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.380s	61.335us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	9.070s	430.608us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	8.520s	2810.857us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.980s	449.611us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.380s	61.335us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.520s	2810.857us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	1.060s	14.542us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.240s	45.145us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.940s	280.786us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.940s	280.786us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.340s	37.136us	5	5	100.00
		keymgr_dpe_csr_rw	1.380s	61.335us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.520s	2810.857us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.600s	326.731us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.340s	37.136us	5	5	100.00
		keymgr_dpe_csr_rw	1.380s	61.335us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.520s	2810.857us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.600s	326.731us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_tl_intg_err	5.250s	214.057us	20	20	100.00
		keymgr_dpe_sec_cm	11.550s	1132.265us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.710s	223.369us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.710s	223.369us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.710s	223.369us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.710s	223.369us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	5.910s	254.148us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	11.550s	1132.265us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	11.550s	1132.265us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.56	97.62	90.14	63.15	75.68	94.61	97.64	17.11

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test keymgr_dpe_smoke has 1 failures.

    • 37.keymgr_dpe_smoke.15623544523360717671949319990838510829837393690041974316431666811316229600574
      Line 3904, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/37.keymgr_dpe_smoke/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---