KMAC/UNMASKED Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	87.850s	5254.518us	100	100	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.350s	38.982us	10	10	100.00
V1	csr_rw	kmac_csr_rw	1.530s	119.638us	40	40	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.190s	5767.851us	10	10	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.230s	546.322us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.410s	1123.436us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.530s	119.638us	40	40	100.00
		kmac_csr_aliasing	10.230s	546.322us	10	10	100.00
V1	mem_walk	kmac_mem_walk	1.130s	15.266us	10	10	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.030s	166.459us	10	10	100.00
V1		TOTAL			230	230	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4189.560s	1384694.154us	100	100	100.00
V2	burst_write	kmac_burst_write	1414.080s	28620.951us	100	100	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	2268.800s	149763.513us	10	10	100.00
		kmac_test_vectors_sha3_256	1954.870s	299455.735us	10	10	100.00
		kmac_test_vectors_sha3_384	1482.190s	119361.100us	10	10	100.00
		kmac_test_vectors_sha3_512	1102.400s	128221.345us	10	10	100.00
		kmac_test_vectors_shake_128	2839.750s	1313269.512us	10	10	100.00
		kmac_test_vectors_shake_256	2190.650s	355882.925us	10	10	100.00
		kmac_test_vectors_kmac	3.390s	394.953us	10	10	100.00
		kmac_test_vectors_kmac_xof	3.450s	286.937us	10	10	100.00
V2	sideload	kmac_sideload	584.760s	23699.445us	100	100	100.00
V2	app	kmac_app	365.430s	14098.644us	100	100	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	296.000s	71823.073us	20	20	100.00
V2	entropy_refresh	kmac_entropy_refresh	360.220s	86556.331us	100	100	100.00
V2	error	kmac_error	496.770s	87395.809us	100	100	100.00
V2	key_error	kmac_key_error	16.500s	1825.880us	100	100	100.00
V2	sideload_invalid	kmac_sideload_invalid	107.230s	10009.455us	95	100	95.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.340s	8578.373us	40	40	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.410s	2181.941us	40	40	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	78.310s	10826.585us	20	20	100.00
V2	lc_escalation	kmac_lc_escalation	57.850s	4007.827us	100	100	100.00
V2	stress_all	kmac_stress_all	2772.740s	148526.640us	100	100	100.00
V2	intr_test	kmac_intr_test	1.220s	114.295us	100	100	100.00
V2	alert_test	kmac_alert_test	1.260s	45.485us	100	100	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.430s	550.615us	40	40	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.430s	550.615us	40	40	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.350s	38.982us	10	10	100.00
		kmac_csr_rw	1.530s	119.638us	40	40	100.00
		kmac_csr_aliasing	10.230s	546.322us	10	10	100.00
		kmac_same_csr_outstanding	3.050s	685.392us	40	40	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.350s	38.982us	10	10	100.00
		kmac_csr_rw	1.530s	119.638us	40	40	100.00
		kmac_csr_aliasing	10.230s	546.322us	10	10	100.00
		kmac_same_csr_outstanding	3.050s	685.392us	40	40	100.00
V2		TOTAL			1475	1480	99.66
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.890s	105.373us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.890s	105.373us	40	40	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.890s	105.373us	40	40	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.890s	105.373us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.650s	219.190us	40	40	100.00
V2S	tl_intg_err	kmac_tl_intg_err	5.750s	763.975us	40	40	100.00
		kmac_sec_cm	80.830s	8554.555us	10	10	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.750s	763.975us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	57.850s	4007.827us	100	100	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	87.850s	5254.518us	100	100	100.00
V2S	sec_cm_key_sideload	kmac_sideload	584.760s	23699.445us	100	100	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.890s	105.373us	40	40	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	80.830s	8554.555us	10	10	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	80.830s	8554.555us	10	10	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	80.830s	8554.555us	10	10	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	87.850s	5254.518us	100	100	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	57.850s	4007.827us	100	100	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	80.830s	8554.555us	10	10	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	348.840s	13598.106us	20	20	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	87.850s	5254.518us	100	100	100.00
V2S		TOTAL			150	150	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	289.600s	4674.670us	16	20	80.00
V3		TOTAL			16	20	80.00
		TOTAL			1871	1880	99.52

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.81	97.69	94.44	100.00	74.38	96.04	97.74	96.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 2.kmac_stress_all_with_rand_reset.10284678845110229629848518978361291539953495656059013636378048019279211615835
      Line 95, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1443276177 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1443276177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.kmac_stress_all_with_rand_reset.107123149045162175280965337530127464771404010638871918846612246969680885917242
      Line 323, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7471175451 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7471175451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 4.kmac_stress_all_with_rand_reset.102641713099373488138852313941729002658602025488260922336926171430136200114361
      Line 325, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9563272046 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 9563272046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 0.kmac_stress_all_with_rand_reset.30628318313954860749452335291597658296998376588665027455341296685466263410838
      Line 187, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 689325943 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 689325943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 23.kmac_sideload_invalid.92283522043798971171395240785059627888755223763392000835046078040755215501634
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10009454708 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7ffca000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10009454708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 25.kmac_sideload_invalid.83690155339786648451769268810313314680804764758606559040180114629809839031560
      Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10143794707 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8933b000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
        UVM_INFO @ 10143794707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 33.kmac_sideload_invalid.577133745192705815428975417463628155615076623884076312473577518204117332541
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10037706742 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfe854000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10037706742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 38.kmac_sideload_invalid.37095521294463871191384414829143735531403917944024857663489988659469360094324
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10105788849 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4b29d000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10105788849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 47.kmac_sideload_invalid.10007390145097810022240807657316403665400927430209352019274652890860736171272
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10106821476 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2230d000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10106821476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---