MBX Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	46.000s	3337.488us	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	26.899us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	12.822us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	4.000s	298.055us	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	76.104us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	62.901us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	12.822us	20	20	100.00
		mbx_csr_aliasing	2.000s	76.104us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	2.000s	43.329us	0	2	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	26.000s	1251.648us	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	25.000s	22482.820us	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	18.000s	552.105us	5	5	100.00
V2	alert_test	mbx_alert_test	3.000s	198.768us	50	50	100.00
V2	intr_test	mbx_intr_test	2.000s	73.797us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.000s	197.710us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.000s	197.710us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	26.899us	5	5	100.00
		mbx_csr_rw	2.000s	12.822us	20	20	100.00
		mbx_csr_aliasing	2.000s	76.104us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	53.556us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	26.899us	5	5	100.00
		mbx_csr_rw	2.000s	12.822us	20	20	100.00
		mbx_csr_aliasing	2.000s	76.104us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	53.556us	20	20	100.00
V2		TOTAL			147	151	97.35
V2S	tl_intg_err	mbx_sec_cm	1.000s	22.925us	5	5	100.00
		mbx_tl_intg_err	3.000s	157.363us	20	20	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			229	233	98.28

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
93.80	96.88	92.43	96.86	91.52	86.12	--	97.01	86.13

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.51180602219932910270978498835168794902843827412722085126436135245598067014995
      Line 185, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 22482819627 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 22482819627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress has 1 failures.

    • 1.mbx_stress.113322001980279262695442837347008157493327552976315107339085683843312367435912
      Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress/latest/run.log

        UVM_ERROR @  43329420 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  43329420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.66771890497624252576330852586973982251536180462654599033030285552774097469942
      Line 100, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @   7642696 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (3723805722 [0xddf4c41a] vs 0 [0x0]) RDATA read data mismatched
        UVM_INFO @   7642696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 1.mbx_stress_zero_delays.62854654143918096632675054285304764192333537682107733194561200665313731613078
      Line 156, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 1268944455 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
        UVM_ERROR @ 1268944455 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
        UVM_INFO @ 1268944455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---