OTBN Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	663.761us	1	1	100.00
V1	single_binary	otbn_single	51.000s	201.955us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	23.679us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	16.090us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	96.309us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	12.000s	24.925us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	47.158us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	16.090us	20	20	100.00
		otbn_csr_aliasing	12.000s	24.925us	5	5	100.00
V1	mem_walk	otbn_mem_walk	42.000s	370.366us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	28.000s	360.427us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	41.000s	92.517us	10	10	100.00
V2	multi_error	otbn_multi_err	55.000s	1852.364us	1	1	100.00
V2	back_to_back	otbn_multi	198.000s	735.391us	10	10	100.00
V2	stress_all	otbn_stress_all	680.000s	4865.836us	10	10	100.00
V2	lc_escalation	otbn_escalate	17.000s	71.870us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	6.000s	31.315us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	44.000s	233.600us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	38.324us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	28.478us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	70.850us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	70.850us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	23.679us	5	5	100.00
		otbn_csr_rw	8.000s	16.090us	20	20	100.00
		otbn_csr_aliasing	12.000s	24.925us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	27.086us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	23.679us	5	5	100.00
		otbn_csr_rw	8.000s	16.090us	20	20	100.00
		otbn_csr_aliasing	12.000s	24.925us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	27.086us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	12.000s	25.474us	10	10	100.00
		otbn_dmem_err	22.000s	87.368us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	41.000s	674.882us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	39.354us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	63.909us	5	5	100.00
		otbn_urnd_err	6.000s	33.825us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	60.523us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	41.897us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	13.000s	63.800us	10	10	100.00
V2S	tl_intg_err	otbn_tl_intg_err	50.000s	317.977us	20	20	100.00
		otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	217.505us	15	20	75.00
V2S	prim_fsm_check	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	663.761us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	22.000s	87.368us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	25.474us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	50.000s	317.977us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	17.000s	71.870us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	25.474us	10	10	100.00
		otbn_dmem_err	22.000s	87.368us	15	15	100.00
		otbn_zero_state_err_urnd	6.000s	31.315us	5	5	100.00
		otbn_illegal_mem_acc	6.000s	60.523us	5	5	100.00
		otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.474us	10	10	100.00
		otbn_dmem_err	22.000s	87.368us	15	15	100.00
		otbn_zero_state_err_urnd	6.000s	31.315us	5	5	100.00
		otbn_illegal_mem_acc	6.000s	60.523us	5	5	100.00
		otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	17.000s	71.870us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.474us	10	10	100.00
		otbn_dmem_err	22.000s	87.368us	15	15	100.00
		otbn_zero_state_err_urnd	6.000s	31.315us	5	5	100.00
		otbn_illegal_mem_acc	6.000s	60.523us	5	5	100.00
		otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	44.462us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	20.319us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	65.000s	1718.562us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	65.000s	1718.562us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	40.379us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	72.956us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	42.760us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	42.760us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	42.718us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	198.000s	735.391us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	110.286us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	51.000s	201.955us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	301.000s	1417.188us	2	5	40.00
V2S		TOTAL			151	163	92.64
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	360.000s	25143.157us	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			563	585	96.24

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.04	99.57	94.89	99.68	93.28	93.89	100.00	96.38	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_sec_wipe_err has 3 failures.

0.otbn_sec_wipe_err.40567933145048487061439785294949816631948484695595667703470503974785178886264
Line 124, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42718267 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42718267 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  42718267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_wipe_err.28960715890247622325639500576968821633553544740888740346579355940599698536295
Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15188228 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15188228 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15188228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_escalate has 2 failures.

11.otbn_escalate.72087147769406110788208636656159877505788872296333196223272859212042151288323
Line 122, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 40343704 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  40343704 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  40343704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

56.otbn_escalate.85815313536841064514940747264304863392118926496893633022014171484788278102096
Line 118, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/56.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 79582437 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  79582437 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  79582437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 3.otbn_stress_all_with_rand_reset.36901035372382970190503813057724057544622281437493351549618875381898818237730
    Line 288, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1860984303 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1860984303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.37950123329849476308152370462167572214530403990310985954426998103781148726046
    Line 164, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105529063 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105529063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 4 failures:
- Test otbn_passthru_mem_tl_intg_err has 4 failures.
  - 0.otbn_passthru_mem_tl_intg_err.39167918256666697505816943227729016936035241184305496374774265829575224500039
    Line 88, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  13985638 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  13985638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_passthru_mem_tl_intg_err.68907674992758470378585494561210913060427002407354642576649668603756556147314
    Line 88, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  16649023 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  16649023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.73415269396839238729614658300267476957599788105285701179714436592305382978255
Line 115, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 266767943 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 266767943 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 266767943 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 266767943 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 266767943 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.31095691434185382693331556211735971241244591068036274671376662876905479528756
Line 101, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 21236123 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 21236123 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 21236123 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 21236123 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 21236123 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 14.otbn_passthru_mem_tl_intg_err.25783588305530576821405979709767745417145644157854264482209633154083708219551
    Line 88, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/14.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  72613478 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  72613478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 3.otbn_escalate.50218946370875909889881018926388299595426891840239841820488697797933985775107
    Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
```
  UVM_FATAL @  42160430 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  42160430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.16162287883332706687979381594520824038450702004589012977560360513204814006630
    Line 206, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 114868717 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 114868717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.56056737590505783238238598531326857902935417996181187238695868913168690350356
    Line 116, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_ERROR @  24767387 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  24767387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,300): Assertion MatchingReqURND_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 15.otbn_escalate.104082219341232486593041995675523971431623770283896219802251382012626419449692
    Line 109, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,300): (time 11745300 PS) Assertion tb.MatchingReqURND_A has failed
  UVM_ERROR @  11745300 ps: (tb.sv:300) [ASSERT FAILED] MatchingReqURND_A
  UVM_INFO @  11745300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```