ROM_CTRL/32KB Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.360s	759.087us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.890s	3978.008us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.140s	1032.683us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.300s	289.052us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.020s	302.918us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.060s	321.692us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.140s	1032.683us	40	40	100.00
		rom_ctrl_csr_aliasing	10.020s	302.918us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.110s	565.494us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.620s	295.351us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.700s	305.021us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	50.190s	65870.597us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	19.850s	2072.910us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	12.890s	2024.157us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.480s	1025.644us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.480s	1025.644us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.890s	3978.008us	10	10	100.00
		rom_ctrl_csr_rw	14.140s	1032.683us	40	40	100.00
		rom_ctrl_csr_aliasing	10.020s	302.918us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.430s	222.554us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.890s	3978.008us	10	10	100.00
		rom_ctrl_csr_rw	14.140s	1032.683us	40	40	100.00
		rom_ctrl_csr_aliasing	10.020s	302.918us	10	10	100.00
		rom_ctrl_same_csr_outstanding	15.430s	222.554us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	53.440s	6357.176us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	578.050s	2495.189us	4	10	40.00
		rom_ctrl_tl_intg_err	125.890s	1621.333us	40	40	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	578.050s	2495.189us	4	10	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	578.050s	2495.189us	4	10	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	578.050s	2495.189us	4	10	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	578.050s	2495.189us	4	10	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.360s	759.087us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.360s	759.087us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.360s	759.087us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	125.890s	1621.333us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
		rom_ctrl_kmac_err_chk	19.850s	2072.910us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	210.880s	3723.724us	37	40	92.50
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	53.440s	6357.176us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	578.050s	2495.189us	4	10	40.00
V2S		TOTAL			121	130	93.08
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	529.670s	5127.756us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			523	532	98.31

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.46	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 4 failures:
  • Test rom_ctrl_sec_cm has 4 failures.

    • 3.rom_ctrl_sec_cm.64101686113639352642408859596185212444350847972522783301269989285783525790241
      Line 554, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 63953986ps failed at 63953986ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 63953986ps failed at 63953986ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 4.rom_ctrl_sec_cm.105604926046402290393241785310027955502039332503665167579675222333730402196444
      Line 108, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 11309951ps failed at 11309951ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11309951ps failed at 11309951ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 2 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 5.rom_ctrl_corrupt_sig_fatal_chk.2102787644738134774643399268923270543206866415876926888387512288659527360394
      Line 91, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 624635480 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 624635480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.rom_ctrl_corrupt_sig_fatal_chk.49381068287531949560569680277516943378823445851980787511688981897585923065534
      Line 101, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 4080527957 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 4080527957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 2 failures:
  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.88450017155003338514549803792968820851970923840985078341271023201092300495786
      Line 172, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 10345189ps failed at 10345189ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 10355606ps failed at 10355606ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • 1.rom_ctrl_sec_cm.7475861587687461213351257014858267356347882933189443407486938978412128735272
      Line 161, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4231454ps failed at 4231454ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 4251454ps failed at 4251454ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'