1f7db17| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.210s | 1072.038us | 20 | 20 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.920s | 63.864us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.830s | 14.866us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.770s | 297.378us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.940s | 63.791us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.280s | 34.785us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.830s | 14.866us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.940s | 63.791us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 11.390s | 40294.438us | 3 | 20 | 15.00 |
| V2 | disabled | rv_timer_disabled | 3.160s | 2113.883us | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 757.870s | 933122.007us | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 757.870s | 933122.007us | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 6.030s | 4579.463us | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.810s | 186.661us | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.910s | 20.680us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.260s | 165.810us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.260s | 165.810us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.920s | 63.864us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.830s | 14.866us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.940s | 63.791us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.050s | 29.695us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.920s | 63.864us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.830s | 14.866us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.940s | 63.791us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.050s | 29.695us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 193 | 210 | 91.90 | |||
| V2S | tl_intg_err | rv_timer_tl_intg_err | 1.520s | 173.040us | 20 | 20 | 100.00 |
| rv_timer_sec_cm | 0.870s | 88.507us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.520s | 173.040us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.930s | 65.710us | 5 | 10 | 50.00 |
| V3 | max_value | rv_timer_max | 0.820s | 195.643us | 0 | 10 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 54.730s | 83881.637us | 16 | 20 | 80.00 |
| V3 | TOTAL | 21 | 40 | 52.50 | |||
| TOTAL | 314 | 350 | 89.71 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.37 | 100.00 | 100.00 | 100.00 | -- | 100.00 | 96.82 | 99.41 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 22 failures:
0.rv_timer_random_reset.79111922392827298398164820865098172993714750453292396443357169050289654576233
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 906898325 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x52e3d704) == 0x1
UVM_INFO @ 906898325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_random_reset.32029302183542945682012058578292459269725893974238717943062835093959841211671
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 62647414 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf4e40704) == 0x1
UVM_INFO @ 62647414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
4.rv_timer_min.21577137463424178000889295110486620655339394189508087790542972747500328143789
Line 75, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/4.rv_timer_min/latest/run.log
UVM_FATAL @ 65710058 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xece51d04) == 0x1
UVM_INFO @ 65710058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_timer_min.5481655080947756437320596390948030706674013678048869070146116533190575864392
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_min/latest/run.log
UVM_FATAL @ 192375592 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6a33a104) == 0x1
UVM_INFO @ 192375592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
0.rv_timer_max.23085581602772184619860447974612057316797178190660715359488274972432813619057
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 195643431 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 195643431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_max.74588940458426361239289183239531047108252768693064444003305376776944554104382
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 47235370 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 47235370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 3 failures:
1.rv_timer_stress_all_with_rand_reset.31877233354083931231831208527329246692945370488899468533982052677254198437243
Line 123, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2261294936 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2261294936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_stress_all_with_rand_reset.13800020726157801125463132538558950223045531059976531962967210647417435815611
Line 270, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2432046689 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2432046689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
5.rv_timer_max.12239270420392052660698409209033737701291179518188976611398021397797274641330
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_max/latest/run.log
UVM_ERROR @ 607154750 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 607154750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
17.rv_timer_stress_all_with_rand_reset.92052617733098520167869385245518149309739080713245492813645049083665655886592
Line 102, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 163435867 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 163435867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---