SPI_DEVICE/1R1W Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: 1f7db17

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	359.260s	138991.454us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.290s	34.243us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	115.453us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.700s	7179.130us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.890s	12831.737us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.080s	168.990us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	115.453us	20	20	100.00
		spi_device_csr_aliasing	17.890s	12831.737us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.930s	10.408us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.500s	60.866us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	21.873us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	4.957us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.910s	7.026us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	9.390s	694.570us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.390s	694.570us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.610s	5524.915us	50	50	100.00
		spi_device_tpm_sts_read	1.420s	335.555us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	37.330s	34619.857us	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	49.260s	29673.191us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	24.840s	7106.265us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	24.840s	7106.265us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	cmd_read_status	spi_device_intercept	35.890s	24183.336us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	35.890s	24183.336us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	35.890s	24183.336us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	35.890s	24183.336us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	35.890s	24183.336us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	41.540s	14286.970us	50	50	100.00
V2	mailbox_command	spi_device_mailbox	106.830s	41938.472us	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	106.830s	41938.472us	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	106.830s	41938.472us	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	73.460s	10905.432us	50	50	100.00
		spi_device_read_buffer_direct	20.480s	9364.674us	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	106.830s	41938.472us	50	50	100.00
		spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	quad_spi	spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	dual_spi	spi_device_flash_all	360.490s	123867.693us	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.750s	7503.614us	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.750s	7503.614us	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	359.260s	138991.454us	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	486.300s	79742.413us	50	50	100.00
V2	stress_all	spi_device_stress_all	678.610s	81783.319us	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	17.613us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.100s	14.525us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.710s	318.303us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.710s	318.303us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.290s	34.243us	5	5	100.00
		spi_device_csr_rw	2.840s	115.453us	20	20	100.00
		spi_device_csr_aliasing	17.890s	12831.737us	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	310.304us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.290s	34.243us	5	5	100.00
		spi_device_csr_rw	2.840s	115.453us	20	20	100.00
		spi_device_csr_aliasing	17.890s	12831.737us	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	310.304us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_tl_intg_err	16.970s	868.045us	20	20	100.00
		spi_device_sec_cm	1.690s	512.730us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.970s	868.045us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	394.800s	717064.812us	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.38	99.11	96.56	83.54	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.44331236208697752143239501695945996303008632773875901097413985820903942486942
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    742897 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[92])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    742897 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    742897 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.113490177829541687942284294555276062475228255542072825386644621854805049531331
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6014976 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[59])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6014976 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6014976 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[955])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.90144412044820522779994902074602060632921001786125855075049462045135468833401
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4820672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x94bf0a [100101001011111100001010] vs 0x0 [0])
        UVM_ERROR @   4878672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd996de [110110011001011011011110] vs 0x0 [0])
        UVM_ERROR @   4966672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaed661 [101011101101011001100001] vs 0x0 [0])
        UVM_ERROR @   5011672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe642f1 [111001100100001011110001] vs 0x0 [0])
        UVM_ERROR @   5054672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x452783 [10001010010011110000011] vs 0x0 [0])
      

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 15.spi_device_flash_mode_ignore_cmds.76585763292725398720634047202219516196412215795679025387195263748633949601396
      Line 114, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 17833865126 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14040064 [0xd63c00] vs 1 [0x1]) CSR last_read_addr compare mismatch act 0xd63c00 != exp 0x1
        tl_ul_fuzzy_flash_status_q[i] = 0x5a1274
        tl_ul_fuzzy_flash_status_q[i] = 0x5a1274
        UVM_INFO @ 19006009771 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 10/12
        UVM_INFO @ 19006009771 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 11/12