SPI_HOST Simulation Results

Friday November 21 2025 17:05:34 UTC

GitHub Revision: `1f7db17`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	62.000s	5861.179us	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	19.705us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	43.991us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	589.462us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	93.520us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	35.873us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	43.991us	20	20	100.00
		spi_host_csr_aliasing	2.000s	93.520us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.991us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	61.298us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	32.000s	23.875us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	54.000s	1927.620us	50	50	100.00
		spi_host_error_cmd	31.000s	29.981us	50	50	100.00
		spi_host_event	142.000s	206061.889us	50	50	100.00
V2	clock_rate	spi_host_speed	32.000s	272.536us	48	50	96.00
V2	speed	spi_host_speed	32.000s	272.536us	48	50	96.00
V2	chip_select_timing	spi_host_speed	32.000s	272.536us	48	50	96.00
V2	sw_reset	spi_host_sw_reset	221.000s	6782.919us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	31.000s	57.970us	50	50	100.00
V2	cpol_cpha	spi_host_speed	32.000s	272.536us	48	50	96.00
V2	full_cycle	spi_host_speed	32.000s	272.536us	48	50	96.00
V2	duplex	spi_host_smoke	62.000s	5861.179us	50	50	100.00
V2	tx_rx_only	spi_host_smoke	62.000s	5861.179us	50	50	100.00
V2	stress_all	spi_host_stress_all	147.000s	14005.990us	50	50	100.00
V2	spien	spi_host_spien	232.000s	13400.580us	50	50	100.00
V2	stall	spi_host_status_stall	768.000s	1000000.000us	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	37.000s	2401.181us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	54.000s	1927.620us	50	50	100.00
V2	alert_test	spi_host_alert_test	31.000s	26.175us	50	50	100.00
V2	intr_test	spi_host_intr_test	6.000s	17.691us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	557.445us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	557.445us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	19.705us	5	5	100.00
		spi_host_csr_rw	2.000s	43.991us	20	20	100.00
		spi_host_csr_aliasing	2.000s	93.520us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	197.616us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	19.705us	5	5	100.00
		spi_host_csr_rw	2.000s	43.991us	20	20	100.00
		spi_host_csr_aliasing	2.000s	93.520us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	197.616us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_sec_cm	32.000s	277.308us	5	5	100.00
		spi_host_tl_intg_err	2.000s	93.626us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	93.626us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	872.000s	100064.020us	8	10	80.00
		TOTAL			835	840	99.40

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.15	96.82	93.35	98.69	94.15	88.02	100.00	95.21	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 2.spi_host_upper_range_clkdiv.7375711792292449779157021103111411702373228611722665546601876583669099248096
    Line 112, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 22.spi_host_status_stall.26969659619234265363005142863670922792745651365174585171873186575203239892467
    Line 2955, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 2 failures:

Test spi_host_speed has 2 failures.

4.spi_host_speed.24969983226660867856414013788988090136865916132189592718709699255790295783000
Line 294, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log

  UVM_FATAL @ 10048696464 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xcdccf3d4, Comparison=CompareOpEq, exp_data=0x0, call_count=45
  UVM_INFO @ 10048696464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.spi_host_speed.4202401838735802615482735654835291443608978957093364703740809314285477352423
Line 220, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/33.spi_host_speed/latest/run.log

  UVM_FATAL @ 10062693710 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x823e2d14, Comparison=CompareOpEq, exp_data=0x0, call_count=33
  UVM_INFO @ 10062693710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 7.spi_host_upper_range_clkdiv.97286399002453261137964909262881886094044092973122232238332542783439429946923
    Line 126, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100064019640 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0xca53494, Comparison=CompareOpEq, exp_data=0x0, call_count=12
  UVM_INFO @ 100064019640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```