1f7db17| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 163.729s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 163.729s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 138.819s | 0.000us | 0 | 20 | 0.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 112.292s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 430.290s | 278.909us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 430.290s | 278.909us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 430.290s | 278.909us | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 38.290s | 10.240us | 0 | 3 | 0.00 |
| chip_sw_example_manufacturer | 162.462s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_example_concurrency | 212.130s | 150.373us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 13.950s | 0.000us | 0 | 3 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 15.930s | 0.000us | 0 | 3 | 0.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 13.100s | 0.000us | 0 | 3 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 13.100s | 0.000us | 0 | 3 | 0.00 |
| V1 | xbar_smoke | xbar_smoke | 39.510s | 67.495us | 100 | 100 | 100.00 |
| V1 | TOTAL | 106 | 151 | 70.20 | |||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 172.477s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 2805.690s | 3578.362us | 1 | 3 | 33.33 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 291.570s | 195.143us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 123.718s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 81.575s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 130.038s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 143.012s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.600s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.600s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 206.573s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 157.936s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 151.162s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 151.162s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 152.160s | 117.005us | 0 | 3 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 147.050s | 117.029us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 384.560s | 272.602us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 15.866s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 16.062s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 490.360s | 658.615us | 2 | 3 | 66.67 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 292.150s | 248.760us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 599.170s | 582.558us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 599.170s | 582.558us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 505.580s | 348.479us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 268.990s | 164.317us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 268.990s | 164.317us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 417.840s | 2271.486us | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 219.710s | 145.477us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 400.960s | 225.703us | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 230.560s | 147.271us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 265.700s | 161.464us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 221.990s | 145.015us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 222.360s | 165.664us | 0 | 3 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 234.640s | 165.664us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 233.420s | 165.632us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 228.420s | 165.632us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 66.060s | 10.280us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 61.840s | 10.200us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 61.400s | 10.100us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 58.890s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 53.140s | 10.200us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 22.349s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 210.400s | 141.887us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 470.590s | 1779.525us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 49.630s | 10.360us | 0 | 3 | 0.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 56.420s | 10.280us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 60.190s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 62.150s | 10.100us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 48.030s | 10.240us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 63.260s | 10.140us | 0 | 3 | 0.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 50.380s | 10.360us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.292s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 16.781s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 15.797s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 1528.820s | 905.683us | 0 | 100 | 0.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 506.540s | 504.230us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 268.990s | 164.317us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 15.597s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 506.540s | 504.230us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 15.843s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 16.276s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 20.752s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 20.061s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 19.407s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 1528.820s | 905.683us | 0 | 100 | 0.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 384.560s | 272.602us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 503.850s | 375.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 411.910s | 267.385us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 433.440s | 289.826us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 229.380s | 144.115us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 1528.820s | 905.683us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 14.940s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 14.957s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 1528.820s | 905.683us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 15.804s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 433.440s | 289.826us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 326.300s | 280.699us | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 17.575s | 0.000us | 0 | 90 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 15.147s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 15.420s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 12.756s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 14.761s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 14.957s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 23.496s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 343.230s | 268.160us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_prim_tl_access | 681.440s | 730.354us | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 490.360s | 658.615us | 2 | 3 | 66.67 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 51.003s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 18.422s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 17.311s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 29.762s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation | 356.950s | 268.175us | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 1275.820s | 1266.532us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.005s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 266.260s | 157.127us | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 61.840s | 10.200us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 240.810s | 145.841us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 230.560s | 147.271us | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 218.210s | 156.379us | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 61.400s | 10.100us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 265.700s | 161.464us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 256.350s | 148.945us | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 286.530s | 172.123us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 53.140s | 10.200us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 356.950s | 268.175us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 52.090s | 10.360us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 333.800s | 198.723us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 221.990s | 145.015us | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 484.020s | 280.880us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 484.020s | 280.880us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 18.691s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 272.390s | 156.794us | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 3519.400s | 1867.945us | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 356.950s | 268.175us | 0 | 3 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 58.890s | 10.180us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 4011.900s | 1459.320us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 66.060s | 10.280us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 400.960s | 225.703us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 400.960s | 225.703us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 400.960s | 225.703us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 508.560s | 265.003us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 1275.820s | 1266.532us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 1275.820s | 1266.532us | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 433.230s | 322.502us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 22.349s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.005s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 1528.820s | 905.683us | 0 | 100 | 0.00 |
| chip_sw_data_integrity_escalation | 151.162s | 0.000us | 0 | 6 | 0.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_otbn_mem_scramble | 508.560s | 265.003us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 356.950s | 268.175us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 433.230s | 322.502us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 208.240s | 161.356us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_otbn_mem_scramble | 508.560s | 265.003us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 356.950s | 268.175us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 433.230s | 322.502us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 208.240s | 161.356us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 15.488s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 23.496s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_prim_tl_access | 681.440s | 730.354us | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 51.003s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 18.422s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 17.311s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 29.762s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 25.325s | 0.000us | 0 | 15 | 0.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 681.440s | 730.354us | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 43.263s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 25.795s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.292s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 66.060s | 10.280us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 61.840s | 10.200us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 61.400s | 10.100us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 58.890s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 53.140s | 10.200us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 22.349s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 210.400s | 141.887us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 220.280s | 143.536us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 220.280s | 143.536us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 216.090s | 138.823us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 213.480s | 136.470us | 0 | 3 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 457.840s | 251.594us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 310.160s | 190.939us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 272.900s | 164.745us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 208.240s | 161.356us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 503.850s | 375.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 503.850s | 375.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 253.060s | 157.107us | 3 | 3 | 100.00 |
| chip_sw_aon_timer_smoketest | 243.770s | 163.260us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 229.280s | 142.931us | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 224.350s | 144.781us | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 231.740s | 174.056us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 299.090s | 182.003us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 284.580s | 171.105us | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 324.080s | 205.430us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 204.390s | 148.065us | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 232.030s | 145.067us | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 313.550s | 248.751us | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 220.950s | 141.618us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 221.970s | 145.480us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 252.930s | 155.680us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 28.862s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 13.950s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 172.477s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 13.890s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 241.530s | 224.089us | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 220.290s | 228.242us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 200.270s | 216.884us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 279.690s | 226.826us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_rv_dm_lc_disabled | 490.360s | 658.615us | 2 | 3 | 66.67 |
| chip_sw_lc_walkthrough_testunlocks | 13.511s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 13.819s | 0.000us | 0 | 3 | 0.00 |
| chip_sw_lc_walkthrough_prod | 26.314s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_prodend | 14.108s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_rma | 20.633s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 13.511s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 771.660s | 789.765us | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 770.470s | 771.364us | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 14.580s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 14.505s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 124.898s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 182.557s | 0.000us | 0 | 3 | 0.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 173.810s | 118.076us | 0 | 30 | 0.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 173.810s | 118.076us | 0 | 30 | 0.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 13.100s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 10.610s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 13.100s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 10.610s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 312.010s | 468.207us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 15.830s | 13.290us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 646.450s | 2835.335us | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 644.630s | 2035.272us | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 150.480s | 85.652us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 2282.820s | 12614.774us | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 3508.850s | 14501.526us | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 201.900s | 231.334us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 176.110s | 246.902us | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 324.110s | 543.982us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 176.110s | 246.902us | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 489.530s | 865.305us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 3466.480s | 16650.760us | 72 | 100 | 72.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 247.840s | 479.854us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 1736.150s | 3933.220us | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 2063.430s | 3974.929us | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 3439.490s | 4692.002us | 99 | 100 | 99.00 |
| xbar_stress_all_with_reset_error | 3221.460s | 6510.093us | 99 | 100 | 99.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 16.272s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 13.588s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 15.705s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 13.646s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 14.007s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 14.542s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 14.642s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 13.281s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 14.848s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 14.551s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 13.362s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 13.444s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 12.316s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 190.612s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 68.916s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 80.422s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 136.057s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 75.588s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 80.542s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 68.617s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 73.763s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 57.944s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 67.342s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 73.066s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 131.777s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 112.137s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 63.542s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 58.029s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 15.764s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 12.304s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 14.350s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 18.382s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 13.068s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 14.077s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 17.659s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 32.917s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 12.850s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 33.177s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 24.203s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 14.245s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 15.394s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 13.332s | 0.000us | 0 | 3 | 0.00 |
| V2 | TOTAL | 1825 | 2405 | 75.88 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 266.930s | 173.980us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 203.640s | 136.460us | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 35.008s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 17.555s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 15.123s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 16.652s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 1528.820s | 905.683us | 0 | 100 | 0.00 |
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 16.336s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 194.610s | 158.268us | 0 | 1 | 0.00 |
| V3 | chip_sw_coremark | chip_sw_coremark | 15.424s | 0.000us | 0 | 1 | 0.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 15.006s | 0.000us | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 35.008s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 17.555s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 15.123s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 10.508s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 16.941s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 16.970s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 14.943s | 0.000us | 0 | 3 | 0.00 |
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 1306.100s | 905.851us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_kat_test | 219.880s | 144.273us | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 205.800s | 141.608us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_0 | 656.990s | 346.708us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_10 | 542.910s | 302.251us | 3 | 3 | 100.00 | ||
| chip_sw_dma_inline_hashing | 292.160s | 191.376us | 3 | 3 | 100.00 | ||
| chip_sw_dma_abort | 257.370s | 192.905us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 14.377s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 14.134s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 17.025s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 14.783s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 14.577s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 13.807s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 16.298s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 14.258s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 13.204s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 25.058s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 289.240s | 187.180us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 635.000s | 425.777us | 3 | 3 | 100.00 | ||
| TOTAL | 1958 | 2639 | 74.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 72.25 | 71.88 | 77.92 | 63.92 | 57.14 | 80.19 | 68.43 | 86.27 |
Job returned non-zero exit code has 399 failures:
0.chip_sw_example_manufacturer.58996932903104338650926453439336547158436130768137338239805019782535519495016
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 145.834s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_manufacturer.94431580220799022650210679650394120084495110045727907095702608071023415320704
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 7.246s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_data_integrity_escalation.50190784647792083507774906947368687007161982707209887726167718016524647963325
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log
Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 137.146s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_data_integrity_escalation.98317084388107667296463631885984409835877609426768699609105447615377777704531
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 16.683s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 4 more failures.
0.chip_sw_sleep_pin_wake.44155425030095949607669866598791166882343447742818298935402958408743149708066
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 191.582s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_wake.65726819161140737541140064086868412241361764126855144200520325049192401135349
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.734s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_sleep_pin_retention.51420326281963379569038144204742183955775069257647872125196962985943308386489
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 143.842s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_retention.8742376941719729228243644868448376917599347322132364417353504827118435046166
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.659s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_uart_tx_rx.37258075384127517496767135366048679983897843146719591992709397960032875247260
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 149.758s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_uart_tx_rx.39839918647860153954898963903292058964434261730273973530674948990876367594339
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.734s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 89 failures:
0.chip_sw_all_escalation_resets.36404629414504051249722053055233000849707624858675232946861117922364519236415
Line 471, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.554000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.554000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_all_escalation_resets.75946751749640170858041527490016673491537248364390829828061095634561074952915
Line 455, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.786000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.786000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 84 more failures.
0.chip_sw_rstmgr_rst_cnsty_escalation.70501201477444635154223074019045672061273425396481013173317829725398629705693
Line 549, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.851000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.851000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_rst_cnsty_escalation.40383856797501013722115392345840842690372284208903451853686959830745257233169
Line 465, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.631000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.631000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 36 failures:
0.chip_sw_otbn_ecdsa_op_irq_jitter_en.39421352620091021632763461623138732580365425728943759723897141283536182768147
Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otbn_ecdsa_op_irq_jitter_en.28230689587238570227338396030907785224616555251072698585969462608470773623165
Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_aes_enc_jitter_en.60827344890523562284834131196425551936701371030379106019394185534748726202120
Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aes_enc_jitter_en.61194892715807056337200917481948973273771983292837176515616801058287076972818
Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_hmac_enc_jitter_en.111335142762516950271401300990090347735840578892040269652988532539805073821362
Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_hmac_enc_jitter_en.75735931858356286931273047052388151658223523304433477086440084018165590076880
Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.78682218993533529793341172115979589313665010320946132660009220681269460894426
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_jitter_en.14205189725357289192544472995939126674755503415424871989896465766670935637226
Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_kmac_mode_kmac_jitter_en.61194932887772503472327413753963023292270140197498693081796857965602999694040
Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_mode_kmac_jitter_en.38859914706473968075554245252042019700462987931117227514878974407197419246721
Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 32 failures:
Test xbar_access_same_device_slow_rsp has 28 failures.
0.xbar_access_same_device_slow_rsp.59988851190278363842254405666983264022310162191401950056915112762203076524162
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
4.xbar_access_same_device_slow_rsp.81536618298138552646614159626234654653962644723490013653500818522543665558942
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
... and 26 more failures.
Test xbar_stress_all_with_rand_reset has 1 failures.
96.xbar_stress_all_with_rand_reset.57156870420967502139608038682182122088596088339936154171526981205061509324283
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/96.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
Test xbar_stress_all_with_reset_error has 1 failures.
98.xbar_stress_all_with_reset_error.60442054353389244922614504854078948893021786122646118113541808267797886133802
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
Test chip_sw_spi_device_pass_through has 2 failures.
0.chip_sw_spi_device_pass_through.36935360528717237293780972869061793783274942254204905881753742864543119178611
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
Job timed out after 60 minutes
1.chip_sw_spi_device_pass_through.83289140739475122750028111781935460410362487745962499747241449130028776462554
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest/run.log
Job timed out after 60 minutes
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 29 failures:
0.chip_tl_errors.20428680456579189023147546455189058451748990053391646397007476671432174664542
Line 229, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.085000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.085000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_tl_errors.106674991928143031567678714997038546152450660291736444698652813098969530729045
Line 229, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 117.964000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 117.964000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 18 failures:
0.chip_sw_rstmgr_cpu_info.97463517978516901074409928933536872549122968690013393882488846070437831554690
Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_cpu_info.33584796814448909171444868849045076691973232467283938631798031509167659416140
Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.472000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_soc_proxy_smoketest.87282856652116267862184241725551954301277991206187903120577933278017810003242
Line 444, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
UVM_ERROR @ 143.536000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 143.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_smoketest.47926230610321754618948922642003769954525086560111558976415169894845968241391
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log
Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
UVM_ERROR @ 143.360000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 143.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_aes_trans.49706121624227018612844038312979270624777583001089775287988869599307078606936
Line 428, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_aes_trans.42041116154317136565319732763546500005585444095613804653680956236223556572596
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_hmac_trans.39438734927600685573157271045124764558402844100755498641601437957950755761642
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_hmac_trans.12948297479663344847349335001349345389103955668513673656831877515938891781830
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_kmac_trans.14919021671233667045373387469923910722939019821929705366096628202281355065730
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.712000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.712000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_kmac_trans.39865401102919602921443551597709402826374454119800252652801223729031988071161
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.632000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.632000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.60355454376517729402810233662243447308323588134072724402261730865687008678704
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.47449886703331092278681230906214418362120059256551394614961615919467344670156
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
0.chip_csr_bit_bash.6665584529155781981612422344609652871193943688308129779340146700764103414349
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_bit_bash.45259195847815137090388257563258815730659248102350637935502402702652706884412
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_csr_aliasing.66775104261185270976071063746888353891820891946663822602607406758869443572841
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_aliasing.67947949051775343750781251399449969971327199294595648811356012652044634000931
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_same_csr_outstanding.23061854882829010240597677332650688260299832175853558274269867228847765763671
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_same_csr_outstanding.64067558200741605080739303123278957535001834841915797643455206005974703573257
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:
0.chip_sw_keymgr_dpe_key_derivation.58318108442997908811658166435050008298098661323310916547600080791377929494995
Line 441, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 268.283000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3048673981793111604255371242024017397426819738223826076502983122954712974794519410893328603942012222178082562801849492813495693582610391425170634512358492 [0x3a359ba6aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3bc632b577f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.283000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation.12949013408655469500254371640089022067564947392250048403043409260083929620617
Line 427, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 267.988000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2969899707074221199020866695750680353624734580474060913187866686474916272953592581330068700543339587305840944243429197586861466754108492490109859532201052 [0x38b4913faae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3bee221ce7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.44439550234613006619139986336426223246129085263103334890638617838898862288725
Line 440, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 268.052000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12369092475483765716558656574993064240200431118122785186728471174919525954846499016418071028176092158896020103740940422024229571579954975373931395227671644 [0xec2add57aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd36a7c6da67f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_prod.82500981712120649557645148823200303897545158297248056998083247137121530179829
Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 268.087000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4335638662454558164875105761264294137382756324581475965829349690941973133086948114853895043479349859275655939388133024736560335036601112472887814915447900 [0x52c8290baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3d49e99fa7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 268.087000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42085) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:
0.chip_jtag_csr_rw.4060133923899073162810313340805318441423835030249392511572570555690478477151
Line 5957, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.042000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42085) { a_addr: 'h30480000 a_data: 'h832c2ae a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h0 a_user: 'h26904 d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.042000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_csr_rw.5483752659860376214938124020757311408302253507530405351764882039841783565907
Line 5957, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.041000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42085) { a_addr: 'h30480000 a_data: 'hc14581ca a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h0 a_user: 'h2694f d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.041000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_jtag_mem_access.5690913290067517460851765599819644468003677575854269723864006157931098526482
Line 5957, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.029000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42085) { a_addr: 'h30480000 a_data: 'h1e733dc2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h1 a_user: 'h248ce d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.029000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_mem_access.30822967709146340019162574625433385050405397674728907193865497026718364242344
Line 5957, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.012000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42085) { a_addr: 'h30480000 a_data: 'h10637251 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h0 a_user: 'h26910 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.012000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 5 failures:
Test chip_sw_otp_ctrl_escalation has 1 failures.
0.chip_sw_otp_ctrl_escalation.65400961717078272591830377169744346663306275948700946123932982829166172748139
Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.268000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.268000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_all_escalation_resets has 4 failures.
15.chip_sw_all_escalation_resets.12818932235254762951075786184051956436902261216524079302365726642094458283740
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.124000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.124000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.chip_sw_all_escalation_resets.34100424983751669565161811543845554157173223035868942895363553567406127913878
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.140000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.140000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 5 failures:
17.chip_sw_all_escalation_resets.84114072307977521229153235456944241243601747259310839898584076072907852006057
Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.140001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
74.chip_sw_all_escalation_resets.27757063741316648692139236100450917108610590761623255156564071536257329705704
Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.140001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
0.chip_sw_example_rom.69769230183945742589440581963410380405658000667990642473815943745368768358856
Line 584, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_example_rom.19884184134395844430764020199253254055609751183543460232837642689786041679830
Line 371, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
0.chip_sw_spi_device_pass_through_collision.104698504379355517180201833161274325200211419375815744958740064721676823624809
Line 454, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 195.143000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 195.143000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_spi_device_pass_through_collision.20547753919827115572066221206411679121337866353549115956092315565698514406011
Line 459, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 170.144000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 170.144000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 3 failures:
0.chip_sw_rstmgr_alert_info.50448758955263268148763937646002254937095952424091327898231904252050462958167
Line 464, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 289.998000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 289.998000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_alert_info.82185546399108428679100450610069635523108523197403818317878358401779867879136
Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 290.130000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 290.130000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
0.chip_sw_soc_proxy_external_wakeup.84566290682037696178526389337854470853443787202899814292161949244141550128209
Line 431, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.823000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.823000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_external_wakeup.54357049924620669497707900025035339605740833789738397606878469355548491420797
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.751000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.751000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 3 failures:
0.chip_sw_soc_proxy_gpios.70542415241833809284222528773979485132415193401189057231468959329150681399120
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.498000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.498000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_gpios.79753920575589707272106039042142208384142784054786444777846507157290468250084
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.470000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.470000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 3 failures:
0.chip_sw_aon_timer_irq.46191941027011392151711547419203485525191086161588299729410870213839094480697
Line 447, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 582.558000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4428 usec which is not in the range 404 usec and 461 usec
UVM_INFO @ 582.558000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_irq.95813991754592656345904797509569119686344804321030366391962592001283057804834
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 475.585000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3314 usec which is not in the range 303 usec and 348 usec
UVM_INFO @ 475.585000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
0.chip_sw_aon_timer_wdog_bite_reset.26301996053372197153017444098629356469265604046926022278548761303645818973962
Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.336000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.336000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_wdog_bite_reset.17184300076738951499779729880463491527773972773992721558745115689221496991673
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.317000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.317000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
0.chip_sw_rv_core_ibex_nmi_irq.36974777364622633431156128311603473542130218646833443084359230483221358308430
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.594000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.594000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_nmi_irq.80465760556939468391495030386286400607661320873443795724031056328687242344439
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.583000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.583000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
0.chip_sw_kmac_app_rom.58700433588342173058627939706988241656325147130693124586224976070612562812407
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_app_rom.93125578993560084602551466041045229262935127873868501443672995523332193377138
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
8.chip_sw_all_escalation_resets.21823938270807339673039979873066887544536533591730218228148397909129090664306
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.845000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.845000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.chip_sw_all_escalation_resets.26511930778471791248102997646248069923532565563858216301520113812964984626870
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.836000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.836000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 2 failures:
1.chip_sw_dma_abort.94973934764435374550407149961844051313569575351730434634902454911842554481251
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log
UVM_FATAL @ 158.048000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 158.048000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_dma_abort.35749373457707980273867818645549150806269801041168544958360592846735297994800
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log
UVM_FATAL @ 160.808000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 160.808000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
2.chip_rv_dm_lc_disabled.29280838654969516354756529157645780682742768464921332592795601636338688774693
Line 223, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 251.998000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x4073c read out mismatch
UVM_INFO @ 251.998000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31867) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.chip_tl_errors.50106083627615736181032474970155094288652915642180919070004988779498519218553
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest/run.log
UVM_ERROR @ 117.967000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31867) { a_addr: 'h40580 a_data: 'h5254c7e2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1850a d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.967000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 1 failures:
0.chip_sw_dma_abort.115730622666962896645360882745480696950718172093936243799454569578861652471491
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 192.905000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 192.905000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'alert_o' has 1 failures:
13.chip_sw_all_escalation_resets.82696561135388662815992415329814897439226052296330830967518944166542993305674
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
Offending 'alert_o'
UVM_ERROR @ 239.068000 us: (prim_alert_receiver.sv:320) [ASSERT FAILED] Alert_A
UVM_INFO @ 239.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 1 failures:
63.chip_sw_all_escalation_resets.106540362562248697603517152859450812168765454798169680290367745940507379535906
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 162.352000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 162.352000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---