AES/MASKED Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: `1ac1583`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	106.303us	2	2	100.00
V1	smoke	aes_smoke	11.000s	845.626us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	56.271us	10	10	100.00
V1	csr_rw	aes_csr_rw	3.000s	108.329us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	1895.851us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	1319.945us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	81.821us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	108.329us	40	40	100.00
		aes_csr_aliasing	4.000s	1319.945us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	11.000s	845.626us	100	100	100.00
		aes_config_error	16.000s	601.116us	100	100	100.00
		aes_stress	46.000s	1984.723us	100	100	100.00
V2	key_length	aes_smoke	11.000s	845.626us	100	100	100.00
		aes_config_error	16.000s	601.116us	100	100	100.00
		aes_stress	46.000s	1984.723us	100	100	100.00
V2	back2back	aes_stress	46.000s	1984.723us	100	100	100.00
		aes_b2b	29.000s	484.163us	100	100	100.00
V2	backpressure	aes_stress	46.000s	1984.723us	100	100	100.00
V2	multi_message	aes_smoke	11.000s	845.626us	100	100	100.00
		aes_config_error	16.000s	601.116us	100	100	100.00
		aes_stress	46.000s	1984.723us	100	100	100.00
		aes_alert_reset	18.000s	1670.493us	100	100	100.00
V2	failure_test	aes_man_cfg_err	7.000s	71.859us	100	100	100.00
		aes_config_error	16.000s	601.116us	100	100	100.00
		aes_alert_reset	18.000s	1670.493us	100	100	100.00
V2	trigger_clear_test	aes_clear	28.000s	1248.927us	99	100	99.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	511.319us	2	2	100.00
V2	reset_recovery	aes_alert_reset	18.000s	1670.493us	100	100	100.00
V2	stress	aes_stress	46.000s	1984.723us	100	100	100.00
V2	sideload	aes_stress	46.000s	1984.723us	100	100	100.00
		aes_sideload	10.000s	390.929us	100	100	100.00
V2	deinitialization	aes_deinit	7.000s	60.828us	100	100	100.00
V2	stress_all	aes_stress_all	67.000s	1277.084us	20	20	100.00
V2	alert_test	aes_alert_test	3.000s	68.238us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	319.231us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	319.231us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	56.271us	10	10	100.00
		aes_csr_rw	3.000s	108.329us	40	40	100.00
		aes_csr_aliasing	4.000s	1319.945us	10	10	100.00
		aes_same_csr_outstanding	3.000s	860.982us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	56.271us	10	10	100.00
		aes_csr_rw	3.000s	108.329us	40	40	100.00
		aes_csr_aliasing	4.000s	1319.945us	10	10	100.00
		aes_same_csr_outstanding	3.000s	860.982us	40	40	100.00
V2		TOTAL			1001	1002	99.90
V2S	reseeding	aes_reseed	19.000s	1004.923us	100	100	100.00
V2S	fault_inject	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	202.244us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	202.244us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	202.244us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	202.244us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	462.719us	40	40	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1709.574us	10	10	100.00
		aes_tl_intg_err	3.000s	186.442us	40	40	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	186.442us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	1670.493us	100	100	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	202.244us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	845.626us	100	100	100.00
		aes_stress	46.000s	1984.723us	100	100	100.00
		aes_alert_reset	18.000s	1670.493us	100	100	100.00
		aes_core_fi	50.000s	10007.499us	136	140	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	202.244us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	85.660us	100	100	100.00
		aes_stress	46.000s	1984.723us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	46.000s	1984.723us	100	100	100.00
		aes_sideload	10.000s	390.929us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	85.660us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	85.660us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	85.660us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	85.660us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	85.660us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	46.000s	1984.723us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	46.000s	1984.723us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	30.000s	2451.853us	98	100	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
		aes_ctr_fi	5.000s	75.656us	100	100	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	30.000s	2451.853us	98	100	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	200000.000us	662	700	94.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	30.000s	2451.853us	98	100	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_ctr_fi	5.000s	75.656us	100	100	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
		aes_ctr_fi	5.000s	75.656us	100	100	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	1670.493us	100	100	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
		aes_ctr_fi	5.000s	75.656us	100	100	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
		aes_ctr_fi	5.000s	75.656us	100	100	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_ctr_fi	5.000s	75.656us	100	100	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	30.000s	2451.853us	98	100	98.00
		aes_control_fi	60.000s	200000.000us	561	600	93.50
		aes_cipher_fi	58.000s	200000.000us	662	700	94.57
V2S		TOTAL			1887	1970	95.79
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	1895.365us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3100	3204	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	98.61	96.47	99.42	95.39	97.99	97.78	98.51	97.99

Failure Buckets

Job timed out after * minutes has 32 failures:
- Test aes_control_fi has 19 failures.
  - 5.aes_control_fi.9808891814388502834507315288091249541598422617046580831948123689975094071030
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 47.aes_control_fi.85382651946244455296790407795713209946300036797220874461216496618323744368038
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/47.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 13 failures.
  - 86.aes_cipher_fi.91640807017273344084449002068694104025238849793746152655714442009267005728193
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 162.aes_cipher_fi.87053570914193059356807604108194848896173531883765013103581885184996385121365
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/162.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 23 failures:
- Test aes_cipher_fi has 23 failures.
  - 0.aes_cipher_fi.55152212287640254262338404567360615133220236801112308269118930130685846133643
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014945452 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014945452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 85.aes_cipher_fi.101533838479992886672422866358822991366786070768698208524992679166916954141921
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/85.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004164694 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004164694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 19 failures:
- Test aes_control_fi has 19 failures.
  - 31.aes_control_fi.96270240804625920656999092062996757228219984554414492392845151588193641634825
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012754815 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012754815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 86.aes_control_fi.6191743991591309571011787955684951678321684462353295714527901407642148786497
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/86.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011238935 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011238935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 14 failures:

Test aes_stress_all_with_rand_reset has 14 failures.

2.aes_stress_all_with_rand_reset.67501001088498593230904018474132450812443408014636360730258543962302672101259
Line 1342, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3181504050 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3181504050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.48751823820464475206026298886259321264901407233793921611253421471875274555673
Line 346, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1773645375 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1773645375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 0.aes_stress_all_with_rand_reset.52855169785977565466758974044148651131478495665294895518539860498909787667684
    Line 151, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  30600388 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  30600388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.aes_stress_all_with_rand_reset.15109291117288468386817018636164473966695336343149535659605135046515242485648
    Line 1274, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1387557205 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1387557205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 23.aes_core_fi.112471026322954844981977602186333195608051446065951738535468853894090771582874
    Line 147, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10046240740 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10046240740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 60.aes_core_fi.15439924824986932090672433293000374794107970669696366213390777553734589199959
    Line 150, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005759389 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005759389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test aes_control_fi has 1 failures.
  - 123.aes_control_fi.93242821420717234464730920445220619581398364898775801836471876048519533438405
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/123.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_cipher_fi has 2 failures.
  - 198.aes_cipher_fi.41967996597643492658753895678615746023644548380699447093688534330033159638513
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/198.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 331.aes_cipher_fi.27111685025489978271567714598399948607130772720068650547977710617702089983050
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/331.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.89401238148028439770157465410533072608146025220786514572323401454328254994538
    Line 626, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4545128761 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 4545128761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.26598954524434859154161912243984291791682750854858728874546249288895890688975
    Line 631, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5747373414 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 5747373414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

11.aes_fi.95505805623952992787453920297504803849564120532390045612153105406697096977654
Line 2225, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/11.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 8068167 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 8058167 PS)
  UVM_ERROR @   8068167 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   8068167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 8.aes_clear.41374042362076842233677954613786374914665849364775966351410171840381095800869
    Line 8370, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_clear/latest/run.log
```
  UVM_FATAL @  85242459 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 da 	 0b 	 76 	 0
                 1 00 	 15 	 26 	 0
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

22.aes_fi.23983608533093810718964152277364327885983280438951848476481628948084182788491
Line 3246, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/22.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 8795235 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8784818 PS)
  UVM_ERROR @   8795235 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   8795235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---