AON_TIMER Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.630s	694.796us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.080s	899.500us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.770s	356.628us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	5.100s	7639.685us	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.540s	639.977us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.460s	388.947us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.770s	356.628us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	639.977us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.290s	311.005us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.780s	430.723us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	59.550s	41446.389us	15	15	100.00
V2	jump	aon_timer_jump	1.750s	749.471us	5	5	100.00
V2	stress_all	aon_timer_stress_all	163.510s	188117.173us	15	15	100.00
V2	alert_test	aon_timer_alert_test	2.010s	509.545us	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.770s	382.541us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.700s	467.962us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.700s	467.962us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.080s	899.500us	5	5	100.00
		aon_timer_csr_rw	1.770s	356.628us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	639.977us	5	5	100.00
		aon_timer_same_csr_outstanding	6.490s	2358.662us	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.080s	899.500us	5	5	100.00
		aon_timer_csr_rw	1.770s	356.628us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	639.977us	5	5	100.00
		aon_timer_same_csr_outstanding	6.490s	2358.662us	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	10.340s	7738.858us	5	5	100.00
		aon_timer_tl_intg_err	11.980s	7966.773us	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	11.980s	7966.773us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	1.520s	525.736us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.070s	667.947us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	13.440s	3686.058us	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	2.420s	619.495us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	13.020s	3986.221us	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	30.500s	15357.099us	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.65	99.09	99.05	98.53	--	98.56	96.67	100.00