CSRNG Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	307.400us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	119.537us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	171.591us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	16.000s	365.537us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	247.246us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	3.000s	24.136us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	171.591us	20	20	100.00
		csrng_csr_aliasing	5.000s	247.246us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	20.000s	1144.754us	200	200	100.00
V2	alerts	csrng_alert	63.000s	5490.305us	500	500	100.00
V2	err	csrng_err	5.000s	41.763us	500	500	100.00
V2	cmds	csrng_cmds	429.000s	43694.311us	50	50	100.00
V2	life cycle	csrng_cmds	429.000s	43694.311us	50	50	100.00
V2	stress_all	csrng_stress_all	658.000s	41607.023us	49	50	98.00
V2	intr_test	csrng_intr_test	3.000s	147.956us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	143.469us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	623.449us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	623.449us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	119.537us	5	5	100.00
		csrng_csr_rw	8.000s	171.591us	20	20	100.00
		csrng_csr_aliasing	5.000s	247.246us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	185.539us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	119.537us	5	5	100.00
		csrng_csr_rw	8.000s	171.591us	20	20	100.00
		csrng_csr_aliasing	5.000s	247.246us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	185.539us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	5.000s	230.444us	5	5	100.00
		csrng_tl_intg_err	7.000s	334.130us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	43.182us	50	50	100.00
		csrng_csr_rw	8.000s	171.591us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	63.000s	5490.305us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	658.000s	41607.023us	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	63.000s	5490.305us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	658.000s	41607.023us	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	63.000s	5490.305us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	7.000s	334.130us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
		csrng_sec_cm	5.000s	230.444us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	20.000s	1144.754us	200	200	100.00
		csrng_err	5.000s	41.763us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	638.000s	39260.410us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1629	1630	99.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.62	98.87	97.25	99.91	96.83	92.08	100.00	95.40	89.78

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
  • Test csrng_stress_all has 1 failures.

    • 33.csrng_stress_all.3338633030029907463900793504853876217787155352502624202512003293386855432711
      Line 172, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/33.csrng_stress_all/latest/run.log

        UVM_ERROR @ 14635084770 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 14635084770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---