DMA Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	32.000s	1446.056us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	33.000s	659.015us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	32.000s	497.466us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	33.222us	5	5	100.00
V1	csr_rw	dma_csr_rw	3.000s	62.632us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	3946.430us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	865.356us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	55.970us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	3.000s	62.632us	20	20	100.00
		dma_csr_aliasing	7.000s	865.356us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	158.000s	22189.329us	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	741.000s	54824.030us	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	373.000s	29657.761us	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	373.000s	29657.761us	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	741.000s	54824.030us	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	1579.000s	1163074.858us	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	373.000s	29657.761us	3	3	100.00
V2	dma_abort	dma_abort	42.000s	4874.146us	5	5	100.00
V2	dma_stress_all	dma_stress_all	346.000s	62323.343us	3	3	100.00
V2	alert_test	dma_alert_test	28.000s	13.001us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	43.820us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	185.930us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	185.930us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	33.222us	5	5	100.00
		dma_csr_rw	3.000s	62.632us	20	20	100.00
		dma_csr_aliasing	7.000s	865.356us	5	5	100.00
		dma_same_csr_outstanding	3.000s	389.492us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	33.222us	5	5	100.00
		dma_csr_rw	3.000s	62.632us	20	20	100.00
		dma_csr_aliasing	7.000s	865.356us	5	5	100.00
		dma_same_csr_outstanding	3.000s	389.492us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	51.000s	359.635us	5	5	100.00
		dma_generic_stress	1579.000s	1163074.858us	5	5	100.00
		dma_handshake_stress	373.000s	29657.761us	3	3	100.00
V2S	dma_config_lock	dma_config_lock	34.000s	1375.036us	15	15	100.00
V2S	tl_intg_err	dma_sec_cm	28.000s	23.211us	5	5	100.00
		dma_tl_intg_err	5.000s	224.868us	20	20	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	195.000s	61351.386us	25	25	100.00
		dma_longer_transfer	32.000s	537.039us	5	5	100.00
		dma_stress_all_with_rand_reset	30.000s	422.206us	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.35	97.38	95.83	96.89	96.04	83.12	92.96	95.97	79.60

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.3665711256370711339912651000007629586261925388290408597013233055449543481919
      Line 90, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  422206107ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  422206107ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---