EDN Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.390s	26.060us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.940s	17.719us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.850s	92.810us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.520s	1253.715us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.140s	67.438us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.440s	54.383us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.850s	92.810us	20	20	100.00
		edn_csr_aliasing	1.140s	67.438us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	244.580s	30809.013us	299	300	99.67
V2	csrng_commands	edn_genbits	244.580s	30809.013us	299	300	99.67
V2	genbits	edn_genbits	244.580s	30809.013us	299	300	99.67
V2	interrupts	edn_intr	1.320s	27.695us	50	50	100.00
V2	alerts	edn_alert	1.690s	98.019us	200	200	100.00
V2	errs	edn_err	1.520s	25.822us	100	100	100.00
V2	disable	edn_disable	1.310s	14.362us	50	50	100.00
		edn_disable_auto_req_mode	1.690s	40.335us	50	50	100.00
V2	stress_all	edn_stress_all	5.040s	212.172us	50	50	100.00
V2	intr_test	edn_intr_test	0.950s	20.800us	50	50	100.00
V2	alert_test	edn_alert_test	2.100s	112.612us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.840s	339.293us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.840s	339.293us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.940s	17.719us	5	5	100.00
		edn_csr_rw	0.850s	92.810us	20	20	100.00
		edn_csr_aliasing	1.140s	67.438us	5	5	100.00
		edn_same_csr_outstanding	1.130s	36.804us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.940s	17.719us	5	5	100.00
		edn_csr_rw	0.850s	92.810us	20	20	100.00
		edn_csr_aliasing	1.140s	67.438us	5	5	100.00
		edn_same_csr_outstanding	1.130s	36.804us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_tl_intg_err	2.050s	123.596us	20	20	100.00
		edn_sec_cm	16.450s	3305.970us	5	5	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.900s	17.999us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.690s	98.019us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	16.450s	3305.970us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	16.450s	3305.970us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	16.450s	3305.970us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	16.450s	3305.970us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.690s	98.019us	200	200	100.00
		edn_sec_cm	16.450s	3305.970us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.690s	98.019us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.050s	123.596us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	9785.660s	10000000.000us	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1111	1130	98.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.39	98.87	94.29	97.02	90.70	96.33	97.56	92.94

Failure Buckets

• Job timed out after * minutes has 16 failures:

  • Test edn_stress_all_with_rand_reset has 16 failures.

    • 2.edn_stress_all_with_rand_reset.6062427982402351457437310211438045881084772390773603177559193461670051117134
      Log /nightly/current_run/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 4.edn_stress_all_with_rand_reset.39037305426220232572102395697578089773206340858466657881196563303878722884674
      Log /nightly/current_run/scratch/master/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 14 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_stress_all_with_rand_reset has 2 failures.

    • 6.edn_stress_all_with_rand_reset.35156607985898772629881171024620601094287493684712197079148798784446066076887
      Line 190, in log /nightly/current_run/scratch/master/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 30.edn_stress_all_with_rand_reset.33045965238695933465207380432774902072219362420224577580199008493382247482758
      Line 200, in log /nightly/current_run/scratch/master/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout edn_reg_block.main_sm_state (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:

  • Test edn_genbits has 1 failures.

    • 180.edn_genbits.12752182320861706966661858768524660094697418519713132314457174231527621454611
      Line 80, in log /nightly/current_run/scratch/master/edn-sim-vcs/180.edn_genbits/latest/run.log

        UVM_FATAL @ 30809013311 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout edn_reg_block.main_sm_state (addr=0xc02b744, Comparison=CompareOpEq, exp_data=0xc1, call_count=16)
        UVM_INFO @ 30809013311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---