HMAC Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.830s	2710.204us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.330s	207.936us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.220s	141.840us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.380s	2342.617us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.770s	1765.219us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	993.460s	512875.735us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.220s	141.840us	20	20	100.00
		hmac_csr_aliasing	8.770s	1765.219us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	91.730s	70874.724us	10	10	100.00
V2	back_pressure	hmac_back_pressure	99.140s	3592.626us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	267.680s	6609.634us	30	30	100.00
		hmac_test_sha384_vectors	575.420s	141067.299us	75	75	100.00
		hmac_test_sha512_vectors	586.490s	122482.727us	75	75	100.00
		hmac_test_hmac256_vectors	15.410s	341.628us	50	50	100.00
		hmac_test_hmac384_vectors	16.980s	4864.124us	60	60	100.00
		hmac_test_hmac512_vectors	19.630s	406.223us	75	75	100.00
V2	burst_wr	hmac_burst_wr	50.410s	977.118us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	1092.920s	11171.112us	10	10	100.00
V2	error	hmac_error	141.090s	2579.498us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	112.830s	30286.727us	10	10	100.00
V2	save_and_restore	hmac_smoke	17.830s	2710.204us	10	10	100.00
		hmac_long_msg	91.730s	70874.724us	10	10	100.00
		hmac_back_pressure	99.140s	3592.626us	25	25	100.00
		hmac_datapath_stress	1092.920s	11171.112us	10	10	100.00
		hmac_burst_wr	50.410s	977.118us	50	50	100.00
		hmac_stress_all	2524.800s	357111.356us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.830s	2710.204us	10	10	100.00
		hmac_long_msg	91.730s	70874.724us	10	10	100.00
		hmac_back_pressure	99.140s	3592.626us	25	25	100.00
		hmac_datapath_stress	1092.920s	11171.112us	10	10	100.00
		hmac_wipe_secret	112.830s	30286.727us	10	10	100.00
		hmac_test_sha256_vectors	267.680s	6609.634us	30	30	100.00
		hmac_test_sha384_vectors	575.420s	141067.299us	75	75	100.00
		hmac_test_sha512_vectors	586.490s	122482.727us	75	75	100.00
		hmac_test_hmac256_vectors	15.410s	341.628us	50	50	100.00
		hmac_test_hmac384_vectors	16.980s	4864.124us	60	60	100.00
		hmac_test_hmac512_vectors	19.630s	406.223us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.830s	2710.204us	10	10	100.00
		hmac_long_msg	91.730s	70874.724us	10	10	100.00
		hmac_back_pressure	99.140s	3592.626us	25	25	100.00
		hmac_datapath_stress	1092.920s	11171.112us	10	10	100.00
		hmac_burst_wr	50.410s	977.118us	50	50	100.00
		hmac_error	141.090s	2579.498us	10	10	100.00
		hmac_wipe_secret	112.830s	30286.727us	10	10	100.00
		hmac_test_sha256_vectors	267.680s	6609.634us	30	30	100.00
		hmac_test_sha384_vectors	575.420s	141067.299us	75	75	100.00
		hmac_test_sha512_vectors	586.490s	122482.727us	75	75	100.00
		hmac_test_hmac256_vectors	15.410s	341.628us	50	50	100.00
		hmac_test_hmac384_vectors	16.980s	4864.124us	60	60	100.00
		hmac_test_hmac512_vectors	19.630s	406.223us	75	75	100.00
		hmac_stress_all	2524.800s	357111.356us	50	50	100.00
V2	stress_all	hmac_stress_all	2524.800s	357111.356us	50	50	100.00
V2	alert_test	hmac_alert_test	0.910s	15.235us	50	50	100.00
V2	intr_test	hmac_intr_test	0.930s	60.083us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.080s	856.387us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.080s	856.387us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.330s	207.936us	5	5	100.00
		hmac_csr_rw	1.220s	141.840us	20	20	100.00
		hmac_csr_aliasing	8.770s	1765.219us	5	5	100.00
		hmac_same_csr_outstanding	2.780s	141.020us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.330s	207.936us	5	5	100.00
		hmac_csr_rw	1.220s	141.840us	20	20	100.00
		hmac_csr_aliasing	8.770s	1765.219us	5	5	100.00
		hmac_same_csr_outstanding	2.780s	141.020us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.490s	433.984us	5	5	100.00
		hmac_tl_intg_err	4.990s	287.587us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.990s	287.587us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.830s	2710.204us	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.820s	303.442us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1219.150s	194055.616us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.660s	121.665us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.17	99.95	96.80	100.00	100.00	99.83	97.61	100.00