I2C Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: `1ac1583`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	71.150s	1910.549us	50	50	100.00
V1	target_smoke	i2c_target_smoke	36.460s	2722.928us	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.060s	48.827us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.090s	141.104us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.230s	544.154us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.820s	41.003us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.550s	29.531us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.090s	141.104us	20	20	100.00
		i2c_csr_aliasing	1.820s	41.003us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	12.260s	1496.658us	1	50	2.00
V2	host_stress_all	i2c_host_stress_all	2632.760s	49386.187us	12	50	24.00
V2	host_maxperf	i2c_host_perf	2771.980s	49920.024us	50	50	100.00
V2	host_override	i2c_host_override	1.050s	102.109us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	271.140s	20655.610us	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	143.500s	2601.353us	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.650s	160.696us	50	50	100.00
		i2c_host_fifo_fmt_empty	22.970s	2072.591us	50	50	100.00
		i2c_host_fifo_reset_rx	11.590s	203.516us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	180.800s	13634.892us	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	35.380s	2116.082us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.260s	491.165us	19	50	38.00
V2	target_glitch	i2c_target_glitch	2.590s	2105.672us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	1356.740s	65660.724us	50	50	100.00
V2	target_maxperf	i2c_target_perf	7.360s	5646.351us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	69.950s	3345.746us	50	50	100.00
		i2c_target_intr_smoke	10.560s	2584.839us	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.520s	281.084us	50	50	100.00
		i2c_target_fifo_reset_tx	2.250s	261.537us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	1500.730s	64462.282us	50	50	100.00
		i2c_target_stress_rd	69.950s	3345.746us	50	50	100.00
		i2c_target_intr_stress_wr	320.680s	20949.196us	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.950s	1539.527us	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	149.170s	4787.423us	45	50	90.00
V2	bad_address	i2c_target_bad_addr	7.770s	3102.916us	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	41.320s	10108.403us	28	50	56.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.140s	9963.428us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.070s	717.511us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	2771.980s	49920.024us	50	50	100.00
		i2c_host_perf_precise	166.540s	6122.072us	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	35.380s	2116.082us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	29.060s	2104.422us	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.130s	570.629us	50	50	100.00
		i2c_target_nack_acqfull_addr	3.500s	954.580us	50	50	100.00
		i2c_target_nack_txstretch	2.290s	409.227us	34	50	68.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	24.050s	663.578us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.580s	514.161us	50	50	100.00
V2	alert_test	i2c_alert_test	0.980s	18.637us	50	50	100.00
V2	intr_test	i2c_intr_test	0.970s	17.096us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.470s	1458.925us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.470s	1458.925us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.060s	48.827us	5	5	100.00
		i2c_csr_rw	1.090s	141.104us	20	20	100.00
		i2c_csr_aliasing	1.820s	41.003us	5	5	100.00
		i2c_same_csr_outstanding	1.390s	425.461us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.060s	48.827us	5	5	100.00
		i2c_csr_rw	1.090s	141.104us	20	20	100.00
		i2c_csr_aliasing	1.820s	41.003us	5	5	100.00
		i2c_same_csr_outstanding	1.390s	425.461us	20	20	100.00
V2		TOTAL			1625	1792	90.68
V2S	tl_intg_err	i2c_sec_cm	1.320s	82.076us	5	5	100.00
		i2c_tl_intg_err	2.570s	194.627us	20	20	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.570s	194.627us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	44.780s	1015.966us	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	5.790s	786.227us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	13.960s	3959.204us	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1805	2042	88.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.17	97.19	89.06	89.66	47.62	93.68	96.41	89.53

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 84 failures:

Test i2c_host_error_intr has 49 failures.

0.i2c_host_error_intr.7933243590167571352978174117775855538376266747921942054775342819171182167567
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  46887721 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  46887721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.20180967771441419680245456173735142771424658423215652995231425503438583553722
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 325528492 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 325528492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 47 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

2.i2c_target_stress_all_with_rand_reset.92157419625176775251873033673446801445308968174692557918366832989105432319813
Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 993988640 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 993988640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.56339286046584757652512085530366865595408034348511710920454480431116669567835
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  27960963 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  27960963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test i2c_host_stress_all has 22 failures.

3.i2c_host_stress_all.112033437314935734803537870032017300870296873610438655045178525811796554164261
Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 66561040257 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 66561040257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_host_stress_all.59013398096661531776297858743939051761832874037660301706106194954300927632393
Line 104, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 259462484 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 259462484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Test i2c_host_mode_toggle has 9 failures.

11.i2c_host_mode_toggle.42177937972857508139960601372746489284248276435587001458886732500664707128342
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  54735687 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  54735687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.i2c_host_mode_toggle.56244182179144652128479526237458415795956141134437359314264390600409669491769
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  18672358 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  18672358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
- Test i2c_target_unexp_stop has 28 failures.
  - 1.i2c_target_unexp_stop.90439217281042608350283684352844211179627968012108367173224900058560342556592
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  77615688 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 189 [0xbd])
  UVM_INFO @  77615688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.14014940972333737648393335309647225786682569478921605682792611007942733436689
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 419883321 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 197 [0xc5])
  UVM_INFO @ 419883321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
- Test i2c_target_hrst has 22 failures.
  - 0.i2c_target_hrst.80211234436806710389478534067926454709006202120264102925968614295230914470212
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10008762796 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10008762796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.73607178764566609697002401847669118564658587396003497079743444508906301705589
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10023140634 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10023140634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 0.i2c_target_unexp_stop.104162912904674756250823457521539003829995940215658003884921003040344368342834
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  82788539 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  82788539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.106618386319591923354856383719242755336677141676732657810968354993033570072048
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 307322394 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 307322394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
- Test i2c_target_nack_txstretch has 16 failures.
  - 1.i2c_target_nack_txstretch.75081652684163151251424622679247872168955312976104011516674408418599610369265
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 308104168 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 308104168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_nack_txstretch.73390974698539585489757876707170787239232308898628112744846950397465979934448
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 275593532 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 275593532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 15 failures:

Test i2c_host_stress_all has 10 failures.

0.i2c_host_stress_all.35105930430019851144720381862573994987405960909124504348643475395584117872379
Line 138, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20441325735 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3458375

1.i2c_host_stress_all.43156292583626423848927358759416447376412200068122169951521753834766056863237
Line 152, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 42925631391 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5963671

... and 8 more failures.

Test i2c_host_mode_toggle has 5 failures.

1.i2c_host_mode_toggle.11076463489677706831543768928399195872928103710362452364580038294781429027693
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 181871542 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @40588

8.i2c_host_mode_toggle.88042498371818792608417647142531108269357968143063121550130140148700430832034
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  67789393 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @42150

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.52344140372964289325311328655851428109951725251593667430558447920304280166304
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1937484954 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1937484954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.101478146242455778931691332204277262841304251564574405735535887248132919034316
Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1237995849 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1237995849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

0.i2c_target_stress_all_with_rand_reset.68273677235586706014087889374566053655185282777830482577354342728523525034898
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 595933271 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 595933271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.11936269640670868910100620754363076302043324324436288070640235929719276482605
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 999569101 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 999569101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:

Test i2c_host_mode_toggle has 12 failures.

0.i2c_host_mode_toggle.43628633891514065155194263153398184785173963747631403679588530815521399079970
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  35065274 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

2.i2c_host_mode_toggle.105530773148508579331524293134760102447085462910405313616946596489440846346179
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 185878828 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

7.i2c_target_unexp_stop.98538842388808553409197058390328851801194905679821309453321353428769452846787
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 191875515 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 191875515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_target_unexp_stop.22288378720744178834023567521010514322279269611724188937989256952896059339822
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1346475908 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1346475908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
- Test i2c_target_stretch has 5 failures.
  - 7.i2c_target_stretch.20034098743220610398376489747063500443538922471335520500096646996345223143176
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10009498995 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10009498995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.i2c_target_stretch.3441681039114038066965659120315709299227215107268337851912282980503442639693
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10048443452 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10048443452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 21.i2c_host_mode_toggle.46869718139898381578034416393863201316705636362876525700082193190990397014394
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  63966397 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xe6a4c794, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  63966397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 42.i2c_host_mode_toggle.101282066206398763572392604195966069141310456806076024267055084752224545012496
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/42.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  94204751 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x6e2fb394, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  94204751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

5.i2c_host_stress_all.33914784221482532317005980238781966342604343470812974251586216949342677710631
Line 122, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 105726504620 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13605619

24.i2c_host_stress_all.82528910689696367781285952796743011803653172197012248005514076539788455183864
Line 114, in log /nightly/current_run/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 25309091671 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13736935

... and 1 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 41.i2c_target_tx_stretch_ctrl.78800282820533641389324117350362616309383717902747096734267279797034075738145
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 45.i2c_target_tx_stretch_ctrl.12388741951481585603537340031391166349989728689650802416189279957958461635578
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 46.i2c_target_fifo_watermarks_tx.34028691825482695474547744393877338809840983574977612188824628165069109435677
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.62813700939733710492598020659112563950918965509079899101189769941471742043968
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 545384753 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 545384753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.206691270407868219305089979121100148579255377675230744177934122189397169763
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2105671541 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2105671541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 1.i2c_target_stress_all_with_rand_reset.36572581056792409665524776354094749982910923712078508824280126025192692149601
    Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 818359201 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 818359201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_stress_all_with_rand_reset.71837672792906211241435588201349117158420744132991404143317288332633474900379
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 445211709 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 445211709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 22.i2c_host_stress_all.114167212194149886412467851424670701296526127947918342040543773268127387334865
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 31.i2c_host_stress_all.34926386711264207897042313135115438288882497394866433235776626493974634852469
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 5.i2c_target_bad_addr.41227959615355822031463743026651351962761201864519717429643702424369370462090
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 20.i2c_host_mode_toggle.1942695514757107541611491189372401196216169620224278615316496431278646431220
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/20.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 23.i2c_host_stress_all.49984420483748502613980325752023992809817354667190731539855590313324823330648
    Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 3232048418 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```