KEYMGR Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: `1ac1583`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.240s	1294.263us	50	50	100.00
V1	random	keymgr_random	51.940s	10809.573us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.380s	119.370us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.270s	19.642us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.300s	669.139us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.980s	1339.179us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.700s	72.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.270s	19.642us	20	20	100.00
		keymgr_csr_aliasing	6.980s	1339.179us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	100.170s	5441.213us	50	50	100.00
V2	sideload	keymgr_sideload	29.600s	1655.987us	49	50	98.00
		keymgr_sideload_kmac	43.840s	3473.833us	50	50	100.00
		keymgr_sideload_aes	28.430s	14880.269us	50	50	100.00
		keymgr_sideload_otbn	56.530s	14126.689us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	30.640s	3155.485us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	12.090s	573.479us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	10.360s	830.272us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	48.420s	6657.146us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	34.570s	7280.180us	48	50	96.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.690s	508.905us	50	50	100.00
V2	stress_all	keymgr_stress_all	351.530s	85723.860us	48	50	96.00
V2	intr_test	keymgr_intr_test	0.990s	14.375us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.630s	118.823us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.030s	1973.259us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.030s	1973.259us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.380s	119.370us	5	5	100.00
		keymgr_csr_rw	1.270s	19.642us	20	20	100.00
		keymgr_csr_aliasing	6.980s	1339.179us	5	5	100.00
		keymgr_same_csr_outstanding	2.530s	287.210us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.380s	119.370us	5	5	100.00
		keymgr_csr_rw	1.270s	19.642us	20	20	100.00
		keymgr_csr_aliasing	6.980s	1339.179us	5	5	100.00
		keymgr_same_csr_outstanding	2.530s	287.210us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
		keymgr_tl_intg_err	9.190s	5287.471us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.230s	283.860us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.230s	283.860us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.230s	283.860us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.230s	283.860us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.270s	719.727us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.190s	5287.471us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.230s	283.860us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	100.170s	5441.213us	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	51.940s	10809.573us	50	50	100.00
		keymgr_csr_rw	1.270s	19.642us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	51.940s	10809.573us	50	50	100.00
		keymgr_csr_rw	1.270s	19.642us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	51.940s	10809.573us	50	50	100.00
		keymgr_csr_rw	1.270s	19.642us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	12.090s	573.479us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	34.570s	7280.180us	48	50	96.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	34.570s	7280.180us	48	50	96.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	51.940s	10809.573us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	10.280s	780.488us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	11.280s	7179.631us	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	12.090s	573.479us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	11.280s	7179.631us	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	11.280s	7179.631us	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	11.280s	7179.631us	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.350s	5354.348us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	11.280s	7179.631us	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.440s	1581.228us	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1082	1110	97.48

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	99.13	98.07	98.37	100.00	99.01	97.72	91.18

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 3.keymgr_stress_all_with_rand_reset.108867489165407418560486272632825020976007815022986296628546073630802134395653
    Line 311, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 208653610 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 208653610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.keymgr_stress_all_with_rand_reset.110691485180106027725341789756965226194905151814978844275203749458617105956294
    Line 342, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 129100383 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 129100383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_sideload has 1 failures.

4.keymgr_sideload.26523064588903348957102667858934576192913819994821232859431039035267296786521
Line 173, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_sideload/latest/run.log

  UVM_ERROR @  52612328 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  52612328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

9.keymgr_stress_all.83436238268972751744342399615549094234940890922484582212464734105642629700154
Line 3350, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 326454484 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 326454484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.keymgr_stress_all.123839394035749067987104196514820881999951643876756799157090500041428120034
Line 341, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all/latest/run.log

  UVM_ERROR @  77780432 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  77780432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_hwsw_invalid_input has 1 failures.

10.keymgr_hwsw_invalid_input.23846747824775725836369751068404931968263965613843573864805793667809019513389
Line 176, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @  12338530 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  12338530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

26.keymgr_lc_disable.74545815159945845181886177280450533864989651555102426367157977747542163395859
Line 158, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  71798985 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  71798985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 2.keymgr_hwsw_invalid_input.101881405699050894856755138868671415302485055103139747687791096892592380146674
    Line 231, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  45971218 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  45971218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_if.sv:380) [keymgr_if] timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 16.keymgr_custom_cm.10095547113395184478548868722862446115078499359905393185266710541079495294155
    Line 345, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 273170226 ps: (keymgr_if.sv:380) [keymgr_if] timeout occurred!
  UVM_INFO @ 273170226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```